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cy7c67300 ez-host? programmable embedded usb host and peripheral controller with automotive aec grade support cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-08015 rev. *k revised july 5, 2011 ez-host features single chip programmable usb dual-role (host/peripheral) controller with two configurable se rial interface engines (sies) and four usb ports support for usb on-the-go (otg) protocol on-chip 48 mhz 16-bit processor with dynamically switchable clock speed configurable io block supporting a variety of io options or up to 32 bits of gene ral purpose io (gpio) 4k x 16 internal masked rom containing built in bios that supports a communication ready state with access to i 2 c? eeprom interface, external rom, uart, or usb 8k x 16 internal ram for code and data buffering extended memory interface port for external sram and rom 16-bit parallel host port interface (hpi) with a dma/mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip sies fast serial port supports from 9600 baud to 2.0m baud spi support in both master and slave on-chip 16-bit dma/mailbox data path interface supports 12 mhz external crystal or clock 3.3v operation automotive aec grade option (?40c to 85c) package option?100-pin tqfp typical applications ez-host is a very powerful and flexible dual role usb controller that supports a wide variety of applications. it is primarily intended to enable host capability in applications such as: set top boxes printers kvm switches kiosks automotive applications wireless access points timer 0 timer 1 watchdog control 4kx16 rom bios 8kx16 ram cy16 16-bit risc core external mem i/f (sram/rom) sie1 usb-a usb-b sie2 usb-a usb-b otg host/ peripheral usb ports d+,d- d+,d- d+,d- d+,d- uart i/f pwm hss i/f i2c eeprom i/f hpi i/f ide i/f spi i/f nreset a[15:0] d[15:0] ctrl[9:0] cy7c67300 gpio [31:0] pll x1 x2 gpio shared input/output pins shared input/output pins vbus, id mobile power booster cy7c67300 block diagram [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 2 of 102 contents introduction ....................................................................... 3 functional overview ........................................................ 3 processor core ........................................................... 3 clocking ....................................................................... 3 memory ....................................................................... 3 interrupts ..................................................................... 3 general timers and watchdog timer ......................... 3 power management ............... .............. .............. ......... 3 interface descriptions ...................................................... 3 usb interface .............................................................. 4 otg interface .............................................................. 5 external memory interface .. ........................................ 6 general purpose io interface (gpio) ......................... 8 uart interface ............................................................ 8 i2c eeprom interface ............. .............. ........... ......... 8 serial peripheral interface .. ......................................... 8 high-speed serial interface ... ..................................... 9 programmable pulse/pwm inte rface .......................... 9 host port interface .................................................... 10 ide interface ............................................................. 10 charge pump interface ............................................. 11 booster interface ....................................................... 12 crystal interface ........................................................ 12 boot configuration interface ...................................... 13 operational modes .................................................... 13 power savings and reset description ........................ 14 power saving mode description ............................... 14 sleep ......................................................................... 14 external (remote) wakeup so urce ........................... 15 power-on-reset description ..... ................................ 15 reset pin ................................................................... 15 usb reset ................................................................. 15 memory map .................................................................... 15 mapping ..................................................................... 15 registers ......................................................................... 17 processor control registers ..................................... 17 external memory registers ....................................... 24 timer registers ......................................................... 26 general usb registers ............................................. 28 usb host only registers .......................................... 30 usb device only registers ... ................................... 39 otg control registers .............................................. 49 gpio registers ......................................................... 50 ide registers ............................................................ 53 hss registers ........................................................... 56 hpi registers ............................................................ 62 spi registers ............................................................ 66 uart registers ........................................................ 74 pwm registers ......................................................... 76 pin diagram ..................................................................... 80 pin descriptions ............................................................. 80 absolute maximum ratings .......................................... 84 operating conditions ..................................................... 84 crystal requirements (xtalin, xtalout) ................. 84 dc characteristics ......................................................... 84 usb transceiver ....................................................... 85 ac timing characteristics ............................................. 86 reset timing ........................................................... 86 clock timing ............................................................. 86 sram read cycle [15] .............................................. 87 sram write cycle [17] .............................................. 88 i2c eeprom timing-serial io .............. ........... ........ 89 hpi (host port interface) wr ite cycle timing ........... 90 hpi (host port interface) read cycle timing ........... 91 ide timing ................................................................. 92 hss byte mode transmit ........................................ 92 hss block mode transmit ........................................ 92 hss byte and block mode receive .................... 92 hardware cts/rts handshake ............................... 93 register summary .......................................................... 93 ordering information ...................................................... 98 ordering code definitions ..... .................................... 98 package diagram ............................................................ 99 acronyms ...................................................................... 100 document conventions ............................................... 100 units of measure ..................................................... 100 document history page ............................................... 101 sales, solutions, and legal information .................... 102 worldwide sales and design s upport ......... ............ 102 products .................................................................. 102 psoc solutions ....................................................... 102 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 3 of 102 introduction ez-host? (cy7c67300) is cypress semiconductor?s first full-speed, low cost multiport host/ peripheral controller. ez-host is designed to easily interface to most high performance cpus to add usb host functionality. ez-host has its own 16-bit risc processor to act as a coprocessor or operate in standalone mode. ez-host also has a programmable io interface block allowing a wide range of interface options. functional overview an overview of the processor core components are presented in this section. processor core ez-host has a general purpose 16-bit embedded risc processor that runs at 48 mhz. clocking ez-host requires a 12 mhz source for clocking. either an external crystal or ttl level oscillator may be used. ez-host has an internal pll that produces a 48 mhz internal clock from the 12 mhz source. memory ez-host has a built in 4k 16 masked rom and an 8k 16 internal ram. the masked rom contains the ez-host bios. the internal ram can be used for program code or data. interrupts ez-host provides 128 interrupt vectors. the first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts. general timers and watchdog timer ez-host has two built in programmable timers and a watchdog timer. all three timers can generate an interrupt to the ez-host. power management ez-host has one main power saving mode, sleep. sleep mode pauses all operations and prov ides the lowest power state. interface descriptions ez-host has a wide variety of interface options for connectivity. with several interface options available, ez-host can act as a seamless data transport between many different types of devices. see table 1 and table 2 on page 4 to understand how the inter- faces share pins and which can coexist. note that some inter- faces have more then one possible port location selectable through the gpio control register [0xc006]. general guidelines for interfaces are as follows: hpi and ide interfaces are mutually exclusive. if 16-bit external memory is required, then hss and spi default locations must be used. i 2 c eeprom and otg do not conf lict with any interfaces. note 1. default interface location. table 1. interface options for gpio pins gpio pins hpi ide pwm hss spi uart i2c otg gpio31 scl/sda gpio30 scl/sda gpio29 otgid gpio28 tx gpio27 rx gpio26 pwm3 cts [1] gpio25 gpio24 int ioready gpio23 nrd ior gpio22 nwr iow gpio21 ncs gpio20 a1 cs1 gpio19 a0 cs0 gpio18 a2 pwm2 rts [1] gpio17 a1 pwm1 rxd [1] gpio16 a0 pwm0 txd [1] gpio15 d15 d15 gpio14 d14 d14 gpio13 d13 d13 gpio12 d12 d12 gpio11 d11 d11 mosi [1] [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 4 of 102 usb interface ez-host has two built in host/peripheral si es and four usb transceivers that meet th e usb 2.0 specification requirements for fu ll and low speed (high speed is not supported). in host mode, ez-host supports four downstre am ports, each support control, interrupt, bulk, and isochronous transfers. in peripheral mode, ez-host supports one peripheral port with eight endpoints for each of the two si es. endpoint 0 is dedicated as the control en dpoint and only supports control transfers. endpoints 1 though 7 support interrupt, bu lk (up to 64 bytes/packet), or isochronous transfers (up to 1023 bytes/pa cket size). ez-host also supports a combination of host and peripheral ports simultaneously as shown in table 3 . gpio10 d10 d10 sck [1] gpio9 d9 d9 nssi [1] gpio8 d8 d8 miso [1] gpio7 d7 d7 gpio6 d6 d6 gpio5 d5 d5 gpio4 d4 d4 gpio3 d3 d3 gpio2 d2 d2 gpio1 d1 d1 gpio0 d0 d0 table 1. interface options for gpio pins (continued) gpio pins hpi ide pwm hss spi uart i2c otg note 2. alternate interface location. table 2. interface options for external memory bus pins mem pins hpi ide pwm hss spi uart i2c otg d15 cts [2] d14 rts [2] d13 rxd [2] d12 txd [2] d11 mosi [2] d10 sck [2] d9 nssi [2] d8 miso [2] d[7:0] a[18:0] control table 3. usb port configuration options port configurations port 1a port 1b port 2a port 2b otg otg ? ? ? otg + 2 hosts otg ? host host otg + 1 host otg ? host ? otg + 1 host otg ? ? host otg + 1 peripheral otg ? peripheral ? otg + 1 peripheral otg ? ? peripheral 4 hosts host host host host 3 hosts any combination of ports 2 hosts any combination of ports 1 host any port [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 5 of 102 usb features usb 2.0-compliant for full and low speed up to four downstream usb host ports up to two upstream usb peripheral ports configurable endpoint buffers (pointer and length), must reside in internal ram up to eight available peripheral endpoints (one control endpoint) supports control, interrupt, bulk, and isochronous transfers internal dma channels for each endpoint internal pull up and pull down resistors internal series termination resistors on usb data lines usb pins otg interface ez-host has one usb port that is compatible with the usb on-the-go supplement to the u sb 2.0 specification. the usb otg port has a various hardware features to support session request protocol (srp) and host negotiation protocol (hnp). otg is only supported on usb port 1a. otg features internal charge pump to supply and control vbus vbus valid status (above 4.4v) vbus status for 2.4v< vbus <0.8v id pin status switchable 2k ohm internal discharge resistor on vbus switchable 500 ohm internal pull up resistor on vbus individually switchable internal pull up and pull down resistors on the usb data lines otg pins 2 hosts + 1 peripheral host host peripheral ? 2 hosts + 1 peripheral host host ? peripheral 2 hosts + 1 peripheral peripheral ? host host 2 hosts + 1 peripheral ? peripheral host host 1 host + 1 peripheral host ? peripheral ? 1 host + 1 peripheral host ? ? peripheral 1 host + 1 peripheral ? host ? peripheral 1 host + 1 peripheral ? host peripheral ? 1 host + 1 peripheral peripheral ? host ? 1 host + 1 peripheral peripheral ? ? host 1 host + 1 peripheral ? peripheral ? host 1 host + 1 peripheral ? peripheral host ? 2 peripherals peripheral ? peripheral ? 2 peripherals peripheral ? ? peripheral 2 peripherals ? peripheral ? peripheral 2 peripherals ? peripheral peripheral ? 1 peripheral any port table 3. usb port configuration options (continued) port configurations port 1a port 1b port 2a port 2b table 4. usb interface pins pin name pin number dm1a 22 dp1a 23 dm1b 18 dp1b 19 dm2a 9 dp2a 10 dm2b 4 dp2b 5 table 5. otg interface pins pin name pin number dm1a 22 dp1a 23 otgvbus 11 otgid 41 cswitcha 13 cswitchb 12 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 6 of 102 external memory interface ez-host provides a robust interfac e to a wide variety of external memory arrays. all available ex ternal memory array locations can contain either code or data. the cy16 risc processor directly addresses a flat memory space from 0x0000 to 0xffff. external memory interface features supports 8-bit or 16-bit sram or rom sram or rom can be used for code or data space direct addressing of sram or rom two external memory mapped page registers external memory access strobes access to external memory is sampled asynchronously on the rising edge of strobes with a minimu m of one wait state cycle. up to seven wait state cycles may be inserted for external memory access. each additional wait st ate cycle stretches the external memory access time by 21 ns (you must be running in internal memory when changing wait states). an external memory device with 12 ns access time is necessary to support 48 mhz code execution. page registers ez-host allows extended data or program code to be stored in external sram, or rom. the total size of extended memory can be up to 512k bytes. the cy16 processor can access extended memory via two address regions of 0x8000-0x9fff and 0xa000-0xbfff. the page register 0xc018 can be used to control the address region 0x8000-0x9fff and the page register 0xc01a controls the address region of 0xa000-0xbfff. figure 1 illustrates that when the nxmemsel pin is asserted the upper cpu address pins are driv en by the contents of the page x registers. merge mode merge modes enabled through the external memory control register [0xc03a] allow combining of external memory regions in accordance with the following: nxmemsel is active from 0x8000 to 0xbfff nxramsel is active from 0x4000 to 0x7fff when ram merge is disabled; nxramsel is active from 0x4000 to 0xbfff when ram merge is enabled nxromsel is active from 0xc100 to 0xdfff when rom merge is disabled; nxromsel is active from 0x8000 to 0xdfff (excluding the 0xc000 to 0xc0ff area) when rom merge is enabled program memory hole description code residing in the 0xc000-0xc0ff address space is not accessible by the cpu. dma to external memory prohibited ez-host supports an internal dma engine to rapidly move data between different functional blocks within the chip. this dma engine is used for sie1, sie2, hpi, spi, hss, and ide but it can only transfer data between the specified block and internal ram or rom. setting up the dma engine to transfer to or from an external memory space might result in internal ram data corruption because the hardware (for example, hss/hpi/sie1/sie2/ide) does not explicitly check the address range. for example, setting up a dma transfer to external address 0x8000 might result in a dma transfer into address 0x0000. external memory related resource considerations: by default a[18:15] are not available for general addressing and are driven high on power up. the upper address enable register must be written appropr iately to enable a[18:15] for general addressing purposes. 47k ohm external pull up on pin a15 for 12 mhz crystal operation. during the 3 ms bios boot procedure the cpu external memory bus is active. rom boot load value 0xc3b6 located at 0xc100. hpi, hss, spi, sie1, sie2, and ide cannot dma to external memory arrays. page 1 banking is always enabled and is in effect from 0x8000 to 0x9fff. page 2 banking is always enabled and is in effect from 0xa000 to 0xbfff. cpu memory bus strobes may wiggle when chip selects are inactive. figure 1. page n registers external address pins logic 0000 + pc[14:0] 1 0 pagex register[5:0] + pc[12:0] nxmemsel pin a[18:0] pc = program counter x = 1 or 2 a = cpu address bus where: page 1 register active range = 8000h to 9fffh page 2 register active range = a000h to bfffh note: nxmemsel pin active range = 8000h to bfffh [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 7 of 102 external memory interface pins external memory interface block diagrams figure 2 illustrates how to connect a 64k 8 memory array (sram/rom) to the ez-host external memory interface. figure 3 illustrates the interface for connecting a 16-bit rom or 16-bit ram to the ez-host external memory interface. in 16-bit mode, up to 256k words of extern al rom or ram are supported. note that the address lines do not map directly. table 6. external memory interface pins pin name pin number nwr 64 nrd 62 nxmemsel (optional ncs) 34 nxromsel (rom ncs) 35 nxramsel (ram ncs) 36 a18 95 a17 96 a16 97 a15 38 a14 33 a13 32 a12 31 a11 30 a10 27 a9 25 a8 24 a7 20 a6 17 a5 8 a4 7 a3 3 a2 2 a1 1 nbel/a0 99 nbeh 98 d15 67 d14 68 d13 69 d12 70 d11 71 d10 72 d9 73 d8 74 d7 76 d6 77 d5 78 d4 79 d3 80 d2 81 d1 82 d0 83 figure 2. interfacing to 64k 8 memory array figure 3. interfacing up to 256k 16 for external code/data table 6. external memory interface pins (continued) pin name pin number ez-host cy7c67300 external memory array 64k x 8 a[15:0] nwr nrd nxramsel a[15:0] we oe ce d[7:0] d[7:0] interfacing to 64k x 8 external memory array ez-host cy7c67300 external memory array up to 256k x 16 a[18:1] nbel nbeh nwr nrd nxmemsel a[17:0] ble we oe ce d[15:0] d[15:0] up to 256k x 16 external code/data (page mode) bhe [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 8 of 102 figure 4 illustrates the interface for connecting an 8-bit rom or 8-bit ram to the ez-host external memory interface. in 8-bit mode, up to 512k bytes of external rom or ram are supported. general purpose io interface (gpio) ez-host has up to 32 gpio signals available. several other optional interfaces use gpio pins as well and may reduce the overall number of available gpios. gpio description all inputs are sampled asynchronously with state changes occurring at a rate of up to two 48 mhz clock cycles. gpio pins are latched directly into registers, a single flip-flop. unused pin descriptions ensure to tristate unused usb pins with the d+ line pulled high through the internal pull up resistor and the d? line pulled low through the internal pull down resistor. configure unused gpio pins as outputs so they are driven low. uart interface ez-host has a built in uart interface. the uart interface supports data rates from 900 to 115.2k baud. it can be used as a development port or for other interface requirements. the uart interface is exposed through gpio pins. uart features supports baud rates of 900 to 115.2k 8-n-1 uart pins. i 2 c eeprom interface ez-host provides a master-only i 2 c interface for external serial eeproms. the serial eeprom can be used to stor e application specific code and data. use the i 2 c interface for loading code out of eeprom, it is not a general i 2 c interface. the i 2 c eeprom interface is a bios implementation and is exposed through gpio pins. refer to the bios documentation for additional details on this interface. i 2 c eeprom features supports eeproms up to 64 kb (512k bit) auto-detection of eeprom size i 2 c eeprom pins serial peripheral interface ez-host provides a spi interface for added connectivity. ez-host may be configured as either an spi master or spi slave. the spi interface can be exposed through gpio pins or the external memory port. spi features master or slave mode operation dma block transfer and pio byte transfer modes full duplex or half duplex data communication 8-byte receive fifo and 8-byte transmit fifo selectable master spi clock rates from 250 khz to 12 mhz selectable master spi clock phase and polarity slave spi signaling synchronization and filtering slave spi clock rates up to 2 mhz maskable interrupts for block and byte transfer modes individual bit transfer for non-byte aligned serial communi- cation in pio mode programmable delay timing for the active/inactive master spi clock auto or manual control for master mode slave select signal complete access to internal memory figure 4. interfacing up to 512k 8 for external code/data table 7. uart interface pins pin name pin number tx 42 rx 43 ez-host cy7c67300 external memory array up to 512k x8 a[18:0] nwr nrd nxmemsel a[18:0] we oe ce d[7:0] d[7:0] up to 512k x 8 external code/data (page mode) table 8. i 2 c eeprom interface pins pin name pin number gpio number small eeprom sck 39 gpio31 sda 40 gpio30 large eeprom sck 40 gpio30 sda 39 gpio31 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 9 of 102 spi pins the spi port has a few different pin location options as shown in ta b l e 9 . the port location is selectable via the gpio control register [0xc006]. high-speed serial interface ez-host provides an hss interface. the hss interface is a programmable serial connection with baud rate from 9600 baud to 2.0m baud. the hss interface supports both byte and block mode operations and also hardware and software handshaking. complete control of ez-host can be accomplished through this interface via an extensible api and communication protocol. the hss interface can be exposed through gpio pins or the external memory port. hss features 8 bits, no parity code programmable baud rate from 9600 baud to 2m baud selectable 1- or 2-stop bit on transmit programmable inter-character gap timing for block transmit 8-byte receive fifo glitch filter on receive block mode transfer directly to/from ez-host internal memory (dma transfer) selectable cts/rts hardware signal handshake protocol selectable xon/xoff software handshake protocol programmable receive interrupt, block transfer done inter- rupts complete access to internal memory hss pins the hss port has a few different pin location options as shown in table 10 . the port location is selectable via the gpio control register [0xc006]. programmable pulse/pwm interface ez-host has four built in pwm output channels. each channel provides a programmable timing generator sequence that can be used to interface to various image sensors or other applications. the pwm interface is exposed through gpio pins. programmable pulse/pwm features four independent programmable waveform generators programmable predefined frequencies ranging from 5.90 khz to 48 mhz configurable polarity continuous and one-shot mode available programmable pulse/pwm pins. table 9. spi interface pins pin name pin number default location nssi 56 or 65 sck 61 mosi 60 miso 66 alternate location nssi 73 sck 72 mosi 71 miso 74 table 10. hss interface pins pin name pin number default location cts 44 rts 53 rxd 54 txd 55 alternate location cts 67 rts 68 rxd 69 txd 70 table 11. pwm interface pins pin name pin number pwm3 44 pwm2 53 pwm1 54 pwm0 55 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 10 of 102 host port interface ez-host has an hpi interface. the hpi interface provides dma access to the ez-host internal memory by an external host, plus a bidirectional mailbox register for supporting high level commu- nication protocols. this port is designed to be the primary high-speed connection to a host processor. complete control of ez-host can be accomplished through this interface via an extensible api and communication protocol. other than the hardware communication protocols, a host processor has identical control over ez-host whether connecting to the hpi or hss port. the hpi interface is exposed through gpio pins. hpi features 16-bit data bus interface 16 mb/s throughput auto-increment of address pointer for fast block mode transfers direct memory access (dma) to internal memory bidirectional mailbox register byte swapping complete access to internal memory complete control of sies through hpi dedicated hpi status register hpi pins the two hpi address pins are used to address one of four possible hpi port registers as shown in ta b l e 1 3 . ide interface ez-host has an ide interface. the ide interface supports pio mode 0-4 as specified in the information technology-at attachment?4 with packet interface extension (ata/atapi-4) specification, t13/1153d rev 18. there is no need for firmware to use programmable wait states. the cpu read/write cycle is automatically extended as needed for direct cpu to ide read/write accesses. the ez-host ide interface also has a block transfer mode that allows ez-host to read /write large blocks of data to/from the ide data register and move it to/from the ez-host on-chip memory directly without intervention of the cpu. the ide interface is exposed through gpio pins. table14on page11 lists the achieved throughput for maximum block mode data transfer rate (with ide_iordy true) for the various ide pio modes. table 12. hpi interface pins [3, 4] pin name pin number int 46 nrd 47 nwr 48 ncs 49 a1 50 a0 52 d15 56 d14 57 d13 58 d12 59 notes 3. hpi_int is for the outgoing mailbox interrupt. 4. hpi strobes are negative logic sampled on rising edge. d11 60 d10 61 d9 65 d8 66 d7 86 d6 87 d5 89 d4 90 d3 91 d2 92 d1 93 d0 94 table 13. hpi addressing hpi a[1:0] a1 a0 hpi data 0 0 hpi mailbox 0 1 hpi address 1 0 hpi status 1 1 table 12. hpi interface pins (continued) [3, 4] [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 11 of 102 ide features programmable io mode 0?4 block mode transfers direct memory access to/from internal memory through the ide data register ide pins charge pump interface vbus for the usb otg port can be produced by ez-host using its built in charge pump and some external components. ensure the circuit connections look similar to the following diagram. component details: d1 and d2: schottky diodes with a current rating greater than 60 ma c1: ceramic capacitor with a capacitance of 0.1 f c2: make capacitor value no more that 6.5 f since that is the maximum capacitance allowed by the usb otg specifications for a dual role device. the minimum value of c2 is 1 f. there are no restrictions on the type of capacitor for c2. if the vbus charge pump circuit is not to be used, cswitcha, cswitchb, and otgvbus can be left unconnected. charge pump features meets otg supplement requirements, see table 134 on page 85 for details. charge pump pins table 14. ide throughput mode ata/atapi-4 min cycle time actual min cycle time ata/atpi-4 max transfer rate actual max transfer rate pio mode 0 600 ns 30t = 625 ns 3.33 mb/s 3.2 mb/s pio mode 1 383 ns 20t = 416.7 ns 5.22 mb/s 4.8 mb/s pio mode 2 240 13t = 270.8 ns 8.33 mb/s 7.38 mb/s pio mode 3 180 ns 10t = 208.3 ns 11.11 mb/s 9.6 mb/s pio mode 4 120 ns 8t = 166.7 ns 16.67 mb/s 12.0 mb/s t = system clock period = 1/48 mhz. table 15. ide interface pins pin name pin number iordy 46 ior 47 iow 48 cs1 50 cs0 52 a2 53 a1 54 a0 55 d15 56 d14 57 d13 58 d12 59 d11 60 d10 61 d9 65 d8 66 d7 86 d6 87 d5 89 d4 90 d3 91 d2 92 d1 93 d0 94 figure 5. charge pump table 16. charge pump interface pins pin name pin number otgvbus 11 cswitcha 13 cswitchb 12 vbus d1 d2 c1 c2 cswitcha cswitchb otgvbus cy7c67300 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 12 of 102 booster interface ez-host has an on chip power booster circuit for use with power supplies that range between 2.7v and 3.6v. the booster circuit boosts the power to 3.3v nominal to supply power for the entire chip. the booster circuit requires an external inductor, diode, and capacitor. during power down mode, the circuit is disabled to save power. figure 6 shows how to connect the booster circuit. component details: l1: inductor with inductance of 10 h and a current rating of at least 250 ma d1: schottky diode with a current rating of at least 250 ma c1: tantalum or ceramic capacitor with a capacitance of at least 2.2 f figure 7 shows how to connect the power supply when the booster circuit is not being used. booster pins crystal interface the recommended crystal circuit to be used with ez-host is shown in figure 8 if an oscillator is used instead of a crystal circuit, connect it to xtalin and leave xtalout unconnected. for further information about the crystal requirements, see ta b l e 132 on page 84 . noted that the clksel pin (pin 38) is sampled after reset to determine what crystal or clock source frequency is used. for normal operation, 12 mhz is requ ired so the clksel pin must have a 47k ohm pull up resistor to v cc. . crystal pins figure 6. power supply connection with booster figure 7. power supply connection without booster boostvcc vswitch vcc avcc c1 d1 l1 3.3v 2.7v to 3.6v power supply boostvcc vswitch vcc avcc 3.0v to 3.6v power supply table 17. charge pump interface pins pin name pin number boostvcc 16 vswitch 14 figure 8. crystal interface table 18. crystal pins pin name pin number xtalin 29 xtalout 28 y1 c1 = 22 pf c2 = 22 pf cy7c67300 xtalin xtalout 12mhz parallel resonant fundamental mode 500uw 20-33pf 5% [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 13 of 102 boot configuration interface ez-host can boot into any one of four modes. the mode it boots into is determined by the ttl voltage level of gpio[31:30] at the time nreset is deasserted. ta b l e 1 9 shows the different boot pin combinations possible. after a reset pin event occurs, the bios bootup procedure executes for up to 3 ms. gpio[31:30] are sampled by the bios during bootup only. after bootup these pins are available to the application as gpios. ensure that gpio[31:30] is pulled high or low as needed using resistors tied to v cc or gnd with resistor values between 5k ohms and 15k ohms. do not tie gpio[31:30] directly to v cc or gnd. note that in standalone mode, the pull ups on those two pins are used for the serial i2c eeprom (if implemented). make sure that the resistors used for these pull ups conform to the serial eeprom manufacturer's requirements. if any mode other then standalone is chosen, ez-host is in coprocessor mode. the device powers up with the appropriate communication interface enabled according to its boot pins and waits idle until a coprocessor communicates with it. see the bios documentation for greater detail of the boot process. operational modes the operational modes are discussed in the following sections. coprocessor mode ez-host can act as a coprocessor to an external host processor. in this mode, an external host processor drives ez-host and is the main processor rather then ez-host?s own 16-bit internal cpu. an external host processor may interface to ez-host through one of the following three interfaces in coprocessor mode: hpi mode, a 16 bit parallel interface with up to 16 mb transfer rate hss mode, a serial interface with up to 2m baud transfer rate spi mode, a serial interface with up to 2 mb/s transfer rate at bootup gpio[31:30] determine which of these three interfaces are used for coprocessor mode. see table 19 for details. bootloading begins from the selected interface after por + 3 ms of bios bootup. standalone mode in standalone mode, there is no external processor connected to ez-host. instead, ez-host?s own internal 16-bit cpu is the main processor and firmware is typically downloaded from an eeprom. optionally, firmware ma y also be downloaded via usb. see table 19 for booting into standalone mode. after booting into standalone mode (gpio[31:30] = ?11?), the following pins are affected: gpio[31:30] are configured as output pins to examine the eeprom contents gpio[28:27] are enabled for debug uart mode gpio[29] is configured for as otgid for otg applications on port1a ? if otgid is logic 1 then port1a (otg) is configured as a usb peripheral ? if otgid is logic 0 then port1a (otg) is configured as a usb host ports 1b, 2a, and 2b default as usb peripheral ports all other pins remain input pins. table 19. boot configuration interface gpio31 (pin 39) gpio30 (pin 40) boot mode 0 0 host port interface (hpi) 0 1 high-speed serial (hss) 1 0 serial peripheral interface (spi, slave mode) 11i 2 c eeprom (standalone mode) [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 14 of 102 minimum hardware requirements for standalone mode ? peripheral only power savings and reset description this sections describes the different modes for resetting the chip and ways to save power. power saving mode description ez-host has one main power saving mode, sleep. for detailed information about sleep mode, see the sleep section that follows. sleep mode is used for usb applications to support usb suspend and non usb applications as the main chip power down mode. in addition, ez-host is capable of slowing down the cpu clock speed through the cpu speed register [0xc008] without affecting other peripheral timing. reducing the cpu clock speed from 48 mhz to 24 mhz reduces the overall current draw by around 8 ma while reducing it from 48 mhz to 3 mhz reduces the overall current draw by approximately 15 ma. sleep sleep mode is the main chip power down mode and is also used for usb suspend. sleep mode is entered by setting the sleep enable (bit 1) of the power control register [0xc00a]. during sleep mode (usb suspend) the following events and states are true: gpio pins maintain their configuration during sleep (in suspend) external memory address pins are driven low xtalout is turned off internal pll is turned off ensure that firmware disables the charge pump (otg control register [0xc098]) thereby ca using otgvbus to drop below 0.2v. otherwise otgvbus only drops to v cc ? (2 schottky diode drops). booster circuit is turned off usb transceivers is turned off cpu goes into suspend mode until a programmable wakeup event figure 9. minimum standalone hardware configuration ? peripheral only ez-host cy7c67300 gpio[30] gpio[31] scl* sda* 10k bootstrap options bootloading firmware *bootloading begins after por + 3ms bios bootup vcc 10k vcc a2 gnd a0 a1 scl sda vcc wp vcc up to 64k x8 eeprom *gpio[31:30] 31 30 up to 2k x8 scl sda >2k x8 to 64k x8 sda scl int. 16k x8 code / data xout xin 12mhz 22pf 22pf nreset reset logic * parallel resonant fundamental mode 500uw 20-33pf 5% vcc, avcc, boostvcc vreg dminus dplus standard-b or mini-b d+ vbus gnd d- shield reserved gnd, agnd, boostgnd pin 38 vcc 47kohm [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 15 of 102 external (remote) wakeup source there are several possible events available to wake ez-host from sleep mode as shown in ta b l e 2 0 . these may also be used as remote wakeup options for usb applications. see the power control register [0xc00a] [r/w] on page 20 for details. upon wakeup, code begins executing within 200 s, the time it takes the pll to stabilize. power-on-reset description the length of the power-on-reset event can be defined by (v cc ramp to valid) + (crystal startup). a typical application might use a 12 ms power-on-reset event = ~7 ms + ~5 ms, respectively. reset pin the reset pin is active low and requires a minimum pulse duration of sixteen 12 mhz clock cycles (1.3 s). a reset event restores all registers to their default por settings. code execution then begins 200 s later at 0xff00 with an immediate jump to 0xe000, the start of bios. refer to bios documentation for additional details. usb reset a usb reset affects registers 0xc090 and 0xc0b0, all other registers remain unchanged. memory map the memory map is discussed in the following sections. mapping the total memory space directly addressable by the cy16 processor is 64k (0x0000-0xffff). program, data, and io are contained within this 64k space. this memory space is byte addressable. figure 10 on page 16 shows the various memory region address locations. internal memory of the internal memory, 15k bytes are allocated for user's program and data. the lower memory space from 0x0000 to 0x04a2 is reserved for interrupt vectors, general purpose registers, usb control registers, stack, and other bios variables. the upper internal memory space contains ez-host control registers from 0xc000 to 0xc0ff and the bios rom itself from 0xe000 to 0xffff. for more information about the reserved lower memory or the bios rom, refer to the programmer?s documentation and/or the bios documentation. during development with the ez-host toolset, leave the lower area of user's space (0x04a4 to 0x1000) available to load the gdb stub. the gdb stub is required to allow the toolset debug access into ez-host. the chip select pins are not active during accesses to internal memory. external memory up to 32 kb of external memory from 0x4000 - 0xbfff is available via one chip select line (nxramsel) with ram merge enabled (bios default). additionally, another 8 kb region from 0xc100 - 0xdfff is available via a second chip select line (nxromsel) giving 40 kb of total available external memory. together with the internal 15 kb, this gives a total of either ~48 kb (one chip select) or ~56 kb (two chip selects) of available memory for either code or data. note that the memory map and pin names (nxramsel/nxromsel) define specific memory regions for ram vs. rom. this allows the bios to look in the upper external memory space at 0xc100 for scan vectors (enabling code to be loaded/executed from rom). if no scan vectors are required in the design (external memory is used exclusively for data), then all external memory regions can be used for ram. similarly, the external memory can be used exclusively for code space (rom). if more external memory is required, ez-host has enough address lines to support up to 512 kb. however, this requires complex code banking/paging schemes via the extended page registers. for further information about setting up the external memory, see the external memory interface on page 6 . table 20. wakeup sources [5, 6] wakeup source (if enabled) event usb resume d+/d? signaling otgvbus level otgid any edge hpi read hss read spi read irq1 (gpio 25) any edge irq0 (gpio 24) any edge notes 5. read data is discarded (dummy data). 6. hpi_int asserts on a usb resume. [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 16 of 102 figure 10. memory map hw int's sw int's 0x0000 - 0x00ff primary registers swap registers usb registers hpi int / mailbox slave setup packet bios user space ~15k internal memory external memory control registers user space 16k user space ~8k 01 extended page 1 user space up to 64 8k banks 01 extended page 2 user space up to 64 8k banks bank selected by 0xc018 bank selected by 0xc01a 0x0100 - 0x011f 0x0120 - 0x013f 0x0140 - 0x0148 0x014a - 0x01ff 0x0200 - 0x02ff lcp variables 0x0300 - 0x030f bios stack 0x0310 - 0x03ff usb slave & otg 0x0400 - 0x04a2 0x04a4 - 0x3fff 0x4000 - 0x7fff 0x8000 - 0x9fff 0xa000 - 0xbfff 0xc100 - 0xdfff 0xc000 - 0xc0ff 0xe000 - 0xffff [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 17 of 102 registers some registers have different functions for a read vs. a write access or usb host vs. usb device mode. therefore, registers of this type have multiple definitions for the same address. the default register values listed in this data sheet may be altered to some other value during the bios initialization. refer to the bios documentation for register initialization information. processor control registers there are nine registers dedicated to general processor control. each of these registers are covered in this section and are summarized in table 21 . cpu flags register [0xc000] [r] register description the cpu flags register is a re ad only register that gives processor flags status. global interrupt enable (bit 4) the global interrupt enable bit indicates if the global interrupts are enabled. 1: enabled 0: disabled negative flag (bit 3) the negative flag bit indicates if an arithmetic operation results in a negative answer. 1: ms result bit is ?1? 0: ms result bit is not ?1? overflow flag (bit 2) the overflow flag bit indicates if an overflow condition occurred. an overflow condition can occur if an arithmetic result was either larger than the destination operand size (for addition) or smaller than the destination operand must allow for subtraction. 1: overflow occurred 0: overflow did not occur carry flag (bit 1) the carry flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction. 1: carry/borrow occurred 0: carry/borrow did not occur zero flag (bit 0) the zero flag bit indicates if an instruction execution resulted in a ?0?. 1: zero occurred 0: zero did not occur table 21. processor control registers register name address r/w cpu flags register 0xc000 r register bank register 0xc002 r/w hardware revision register 0xc004 r cpu speed register 0xc008 r/w power control register 0xc00a r/w interrupt enable register 0xc00e r/w breakpoint register 0xc014 r/w usb diagnostic register 0xc03c w memory diagnostic register 0xc03e w table 22. cpu flags register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved global interrupt enable negative flag overflow flag carry flag zero flag read/write - - - r r r r r default 0 0 0 x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 18 of 102 bank register [0xc002] [r/w] register description the bank register maps registers r0?r15 into ram. the eleven m sbs of this register are used as a base address for registers r0?r15. a register address is automatically generated by: 1. shifting the four lsbs of the register address left by 1. 2. oring the four shifted bits of the register address with the twelve msbs of the bank register. 3. forcing the lsb to zero. for example, if the bank register is left at its default valu e of 0x0100, and r2 is read, then the physical address 0x0102 is r ead. refer to table 24 for details. address (bits [15:4]) the address field is used as a base address for all register addresses to start from. reserved write all reserved bits with ?0?. hardware revision register [0xc004] [r] register description the hardware revision register is a read on ly register that indicates the silicon revi sion number. the first silicon revision i s represented by 0x0101. this number is increased by one for each new silicon revision. revision (bits [15:0]) the revision field contains the silicon revision number. table 23. bank register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field ...address reserved read/write r/w r/w r/w - - - - - default 0 0 0 x x x x x table 24. bank register example register hex value binary value bank 0x0100 0000 0001 0000 0000 r14 0x000e << 1 = 0x001c 0000 0000 0001 1100 ram location 0x011c 0000 0001 0001 1100 table 25. revision register bit # 15 14 13 12 11 10 9 8 field revision... read/write r r r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...revision read/write r r r r r r r r default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 19 of 102 cpu speed register [0xc008] [r/w] register description the cpu speed register allows the processor to operate at a user selected speed. this register only affects the cpu, all other peripheral timing is still based on the 48 mhz system clock (unle ss otherwise noted). cpu speed (bits[3:0]) the cpu speed field is a divisor that selects the operating speed of the processor as defined in ta b l e 2 7 . reserved write all reserved bits with ?0?. table 26. cpu speed register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved cpu speed read/write - - - - r/w r/w r/w r/w default 0 0 0 0 1 1 1 1 table 27. cpu speed definition cpu speed [3:0] processor speed 0000 48 mhz/1 0001 48 mhz/2 0010 48 mhz/3 0011 48 mhz/4 0100 48 mhz/5 0101 48 mhz/6 0110 48 mhz/7 0111 48 mhz/8 1000 48 mhz/9 1001 48 mhz/10 1010 48 mhz/11 1011 48 mhz/12 1100 48 mhz/13 1101 48 mhz/14 1110 48 mhz/15 1111 48 mhz/16 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 20 of 102 power control register [0xc00a] [r/w] register description the power control register controls the power down and wakeup options. either the sleep mode or the halt mode options can be selected. all other writable bits in this register can be used as a wakeup source while in sleep mode. host/device 2b wake enable (bit 15) the host/device 2b wake enable bit enables or disables a wakeup condition to occur on a host/device 2b transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 2b transition 0: disable wakeup on host/device 2b transition host/device 2a wake enable (bit 14) the host/device 2a wake enable bit enables or disables a wakeup condition to occur on an host/device 2a transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 2a transition 0: disable wakeup on host/device 2a transition host/device 1b wake enable (bit 13) the host/device 1b wake enable bit enables or disables a wakeup condition to occur on an host/device 1b transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 1b transition 0: disable wakeup on host/device 1b transition host/device 1a wake enable (bit 12) the host/device 1a wake enable bit enables or disables a wakeup condition to occur on an host/device 1a transition. this wakeup from the sie port does not cause an interrupt to the on-chip cpu. 1: enable wakeup on host/device 1a transition 0: disable wakeup on host/device 1a transition otg wake enable (bit 11) the otg wake enable bit enables or disables a wakeup condition to occur on either an otg vbus_valid or otg id transition (irq20). 1: enable wakeup on otg vbus valid or otg id transition 0: disable wakeup on otg vbus valid or otg id transition hss wake enable (bit 9) the hss wake enable bit enables or disables a wakeup condition to occur on an hss rx serial input transition. the processor may take several hundreds of microseconds before being operational after wakeup. therefore, the incoming data byte that causes the wakeup is discarded. 1: enable wakeup on hss rx serial input transition 0: disable wakeup on hss rx serial input transition spi wake enable (bit 8) the spi wake enable bit enables or disables a wakeup condition to occur on a falling spi_nss input transition. the processor may take several hundreds of microseconds before being opera- tional after wakeup. therefore, the incoming data byte that causes the wakeup is discarded. 1: enable wakeup on falling spi nss input transition 0: disable spi_nss interrupt hpi wake enable (bit 7) the hpi wake enable bit enables or disables a wakeup condition to occur on an hpi interface read. 1: enable wakeup on hpi interface read 0: disable wakeup on hpi interface read gpi wake enable (bit 4) the gpi wake enable bit enables or disables a wakeup condition to occur on a gpio(25:24) transition. 1: enable wakeup on gpio(25:24) transition 0: disable wakeup on gpio(25:24) transition table 28. power control register bit # 15 14 13 12 11 10 9 8 field host/device 2b wake enable host/device 2a wake enable host/device 1b wake enable host/device 1a wake enable otg wake enable reserved hss wake enable spi wake enable read/write r/w r/w r/w r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable read/write r/w - - r/w - r r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 21 of 102 boost 3v ok (bit 2) the boost 3v ok bit is a read only bit that returns the status of the otg boost circuit. 1: boost circuit not ok and internal voltage rails are below 3.0v 0: boost circuit ok and internal voltage rails are at or above 3.0v sleep enable (bit 1) setting this bit to ?1? immediately initiates sleep mode. while in sleep mode, the entire chip is paused, achieving the lowest standby power state. all operations are paused, the internal clock is stopped, the booster circuit and otg vbus charge pump are all powered down, and the usb transceivers are powered down. all counters and timers are paused but retain their values; enabled pwm outputs freeze in their current states. sleep mode exits by any activity selected in this register. when sleep mode ends, instruction exec ution resumes within 0.5 ms. 1: enable sleep mode 0: no function halt enable (bit 0) setting this bit to ?1? immediately initiates halt mode. while in halt mode, only the cpu is stopped. the internal clock still runs and all peripherals still operate, including the usb engines. the power saving using halt in most cases is minimal, but in appli- cations that are very cpu intensive the incremental savings may provide some benefit. the halt state is exited when any enabled interrupt is triggered. upon exiting the halt state, one or two instructions immediately following the halt instruction may be executed before the waking interrupt is serviced (you may want to follow the halt instruction with two nops). 1: enable halt mode 0: no function reserved write all reserved bits with ?0?. interrupt enable register [0xc00e] [r/w] register description the interrupt enable register allows control of the hardware interrupt vectors. otg interrupt enable (bit 12) the otg interrupt enable bit enables or disables the otg id/otg4.4v valid hardware interrupt. 1: enable otg interrupt 0: disable otg interrupt spi interrupt enable (bit 11) the spi interrupt enable bit enables or disables the following three spi hardware interrupts: spi tx, spi rx, and spi dma block done. 1: enable spi interrupt 0: disable spi interrupt host/device 2 interrupt enable (bit 9) the host/device 2 interrupt enable bit enables or disables all of the following host/device 2 hardware interrupts: host 2 usb done, host 2 usb sof/eop, host 2 wakeup/insert/remove, device 2 reset, device 2 sof/ eop or wakeup from usb, device 2 endpoint n. 1: enable host 2 and device 2 interrupt 0: disable host 2 and device 2 interrupt host/device 1 interrupt enable (bit 8) the host/device 1 interrupt enable bit enables or disables all of the following host/device 1 hardware interrupts: host 1 usb done, host 1 usb sof/eop, host 1 wakeup/insert/remove, device 1 reset, device 1 sof/ eop or wakeup from usb, device 1endpoint n. 1: enable host 1 and device 1 interrupt 0: disable host 1 and device 1 interrupt table 29. interrupt enable register bit # 15 14 13 12 11 10 9 8 field reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable read/write - - - r/w r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable read/write r/w r/w r/w - r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 22 of 102 hss interrupt enable (bit 7) the hss interrupt enable bit enables or disables the following high-speed serial interface hardware interrupts: hss block done and hss rx full. 1: enable hss interrupt 0: disable hss interrupt in mailbox interrupt enable (bit 6) the in mailbox interrupt enable bit enables or disables the hpi: incoming mailbox hardware interrupt. 1: enable mbxi interrupt 0: disable mbxi interrupt out mailbox interrupt enable (bit 5) the out mailbox interrupt enable bit enables or disables the hpi: outgoing mailbox hardware interrupt. 1: enable mbxo interrupt 0: disable mbxo interrupt uart interrupt enable (bit 3) the uart interrupt enable bit enables or disables the following uart hardware interrupts: uart tx, and uart rx. 1: enable uart interrupt 0: disable uart interrupt gpio interrupt enable (bit 2) the gpio interrupt enable bit enables or disables the general purpose io pins interrupt (see the gpio control register [0xc006] [r/w] on page 51 ). when the gpio bit is reset, all pending gpio interrupts are also cleared 1: enable gpio interrupt 0: disable gpio interrupt timer 1 interrupt enable (bit 1) the timer 1 interrupt enable bit enables or disables the timer1 interrupt enable. when this bit is reset, all pending timer 1 inter- rupts are cleared. 1: enable tm1 interrupt 0: disable tm1 interrupt timer 0 interrupt enable (bit 0) the timer 0 interrupt enable bit enables or disables the timer0 interrupt enable. when this bit is reset, all pending timer 0 inter- rupts are cleared. 1: enable tm0 interrupt 0: disable tm0 interrupt reserved write all reserved bits with ?0?. breakpoint register [0xc014] [r/w] register description the breakpoint register holds the breakpoint address. when the program counter matches this address, the int127 interrupt occurs. to clear this interrupt, write a zero value to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. table 30. breakpoint register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 23 of 102 usb diagnostic register [0xc03c] [r/w] register description the usb diagnostic register pr ovides control of diagnostic modes. it is intended for use by device characterization tests, not for normal operations. this register is read/write by the on-chip cpu but is write-only via the hpi port. port 2b diagnostic enable (bit 15) the port 2b diagnostic enable bit enables or disables port 2b for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions port 2a diagnostic enable (bit 14) the port 2a diagnostic enable bit enables or disables port 2a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions port 1b diagnostic enable (bit 13) the port 1b diagnostic enable bit enables or disables port 1b for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions port 1a diagnostic enable (bit 12) the port 1a diagnostic enable bit enables or disables port 1a for the test conditions selected in this register. 1: apply any of the following enabled test conditions: j/k, dck, se0, rsf, rsl, prd 0: do not apply test conditions pull-down enable (bit 6) the pull-down enable bit enables or disables full-speed pull down resistors (pull down on both d+ and d?) for testing. 1: enable pull down resistors on both d+ and d? 0: disable pull down resistors on both d+ and d? ls pull-up enable (bit 5) the ls pull-up enable bit enables or disables a low-speed pull up resistor (pull up on d?) for testing. 1: enable low-speed pull up resistor on d? 0: pull-up resistor is not connected on d? fs pull-up enable (bit 4) the fs pull-up enable bit enables or disables a full-speed pull up resistor (pull up on d+) for testing. 1: enable full-speed pull up resistor on d+ 0: pull up resistor is not connected on d+ force select (bits [2:0]) the force select field bit selects several different test condition states on the data lines (d+/d?). refer to table 32 for details. reserved write all reserved bits with ?0?. table 31. usb diagnostic register bit # 15 14 13 12 11 10 9 8 field port 2b diagnostic enable port 2a diagnostic enable port 1b diagnostic enable port 1a diagnostic enable reserved... read/write r/w r/w r/w r/w - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select read/write - r/w r/w r/w - r/w r/w r/w default 0 0 0 0 0 0 0 0 table 32. force select definition force select [2:0] data line state 1xx assert se0 01x toggle jk 001 assert j 000 assert k [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 24 of 102 memory diagnostic register [0xc03e] [w] register description the memory diagnostic register provides control of diagnostic modes. memory arbitr ation select (bits[10:8]) the memory arbitration select field is defined in ta b l e 3 4 . monitor enable (bit 0) the monitor enable bit enables or disables monitor mode. in monitor mode the internal address bus is echoed to the external address pins. 1: enable monitor mode 0: disable monitor mode reserved write all reserved bits with ?0?. external memory registers there are four registers dedicated to controlling the external memory interface. each of these registers are covered in this section and are summarized in table 35 . table 33. memory diagnostic register bit # 15 14 13 12 11 10 9 8 field reserved memory arbitration select read/write - - - - - w w w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved monitor enable read/write - - - - - - - w default 0 0 0 0 0 0 0 0 table 34. memory arbitration select memory arbitration select [3:0] memory arbitration timing 111 1/8, 7 of every 8 cycles dead 110 2/8, 6 of every 8 cycles dead 101 3/8, 5 of every 8 cycles dead 100 4/8, 4 of every 8 cycles dead 011 5/8, 3 of every 8 cycles dead 010 6/8, 2 of every 8 cycles dead 001 7/8, 1 of every 8 cycles dead 000 8/8, all cycles available table 35. external memory control registers register name address r/w extended page 1 map register 0xc018 r/w extended page 2 map register 0xc01a r/w upper address enable register 0xc038 r/w external memory control register 0xc03a r/w [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 25 of 102 extended page n map register [r/w] extended page 1 map register 0xc018 extended page 2 map register 0xc01a register description the extended page n map regis ter contains the page n high-order address bits. these bits are always appended to accesses to the page n memory mapped space. address (bits [15:0]) the address field contains the high-order bits 28 to 13 of the page n address. the address pins [8:0] (page n address [21:13]) reflect the content of this register when the cpu accesses the address 0x8000-0x9fff. for the sram mode, the address pin on [4:0] (page n address [17:13]) is used. set bit [8] (page n address [21]) to ?0?, so that page n reads/writes access external areas (sram, rom or periph- erals). nxmemsel is the external chip select for this space. upper address enable register [0xc038] [r/w] register description the upper address enable regist er enables/disables the four most significant bits of the external address a[18:15]. this register defaults to having the upper address disabled. note that on power up, pins a[18:15] are driven high. upper address enable (bit 3) the upper address enable bit enables/disables the four most significant bits of the external address a[18:15]. 1: enable a[18:15] of the external memory interface for general addressing. 0: disable a[18:15], not available. reserved write all reserved bits with ?0?. table 36. extended page n map register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 37. external memory control register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field reserved upper address enable reserved read/write - - - - r/w default x x x x 0 x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 26 of 102 external memory control r egister [0xc03a] [r/w] register description the external memory control register provides control of wait states for the external sram or rom. all wait states are based off of 48 mhz. xram merge enable (bit 13) the xram merge enable bit enabl es or disables the ram merge feature. when the ram merge feature is enabled, the nxramsel is active whenever the nxmemsel is active. 1: enable ram merge 0: disable ram merge xrom merge enable (bit 12) the xrom merge enable bit enables or disables the rom merge feature. when the rom merge feature is enabled, the nxromsel is active whenever the nxmemsel is active. 1: enable rom merge 0: disable rom merge xmem width select (bit 11) the xmem width select bit selects the extended memory width. 1: extended memory = 8 0: extended memory = 16 xmem wait select (bits [10:8]) the xmem wait select field selects the extended memory wait state from 0 to 7. xrom width select (bit 7) the xrom width select bit selects the external rom width. 1: external memory = 8 0: external memory = 16 xrom wait select (bits[6:4]) the xrom wait select field selects the external rom wait state from 0 to 7. xram width select (bit 3) the xram width select bit selects the external ram width. 1: external memory = 8 0: external memory = 16 xram wait select (bits[2:0]) the xram wait select field selects the external ram wait state from 0 to 7. reserved write all reserved bits with ?0?. timer registers there are three registers dedicated to timer operations. each of these registers are discussed in this section and are summarized in table 39 . table 38. external memory control register bit # 15 14 13 12 11 10 9 8 field reserved xram merge enable xrom merge enable xmem width select xmem wait select read/write - - r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field xrom width select xrom wait select xram width select xram wait select read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x table 39. timer registers register name address r/w watchdog timer register 0xc00c r/w timer 0 register 0xc010 r/w timer 1 register 0xc012 r/w [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 27 of 102 watchdog timer register [0xc00c] [r/w] register description the watchdog timer register provides status and control over the watchdog timer. the watchdog timer can also interrupt the processor. timeout flag (bit 5) the timeout flag bit indicates if the watchdog timer expired. the processor can read this bit after exiting a reset to determine if a watchdog timeout occurred. this bit is cleared on the next external hardware reset. 1: watchdog timer expired. 0: watchdog timer did not expire. period select (bits [4:3]) the period select field is defined in table 41 . if this time expires before the reset strobe bit is set, the internal processor is reset. lock enable (bit 2) the lock enable bit does not allow any writes to this register until a reset. in doing so the watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the wdt enable bit is ignored). 1: watchdog timer permanently set 0: watchdog timer not permanently set wdt enable (bit 1) the wdt enable bit enables or disables the watchdog timer. 1: enable watchdog timer operation 0: disable watchdog timer operation reset strobe (bit 0) the reset strobe is a write-only bit that resets the watchdog timer count. set this bit to ?1? before the count expires to avoid a watchdog trigger 1: reset count reserved write all reserved bits with ?0?. table 40. watchdog timer register bit # 15 14 13 12 11 10 9 8 field reserved... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved timeout flag period select lock enable wdt enable reset strobe read/write r/w r/w r/w r/w r/w r/w r/w w default 0 0 0 0 0 0 0 0 table 41. period select definition period select[4:3] wdt period value 00 1.4 ms 01 5.5 ms 10 22.0 ms 11 66.0 ms [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 28 of 102 timer n register [r/w] timer 0 register 0xc010 timer 1 register 0xc012 register description the timer n register sets the timer n count. both timer 0 and timer 1 decrement by one every 1 s clock tick. each can provide an interrupt to the cpu when the timer reaches zero. count (bits [15:0]) the count field sets the timer count. general usb registers there is one set of registers dedi cated to general usb control. this set consists of two identical registers: one for host/device port 1 and one for host/device port 2. this register set has functions for both usb host and usb peripheral options and is covered in this section and summarized in table 43 . usb host only registers are covered in uart interface on page 8 , and usb device only registers are covered in external memory registers on page 24 . usb n control register [r/w] usb 1 control register 0xc08a usb 2 control register 0xc0aa register description the usb n control register is used in both host and device mode. it monitors and controls the sie and the data lines of the usb ports. this register can be accessed by the hpi interface. port b d+ status (bit 15) the port b d+ status bit is a read only bit that indicates the value of data+ on port b. 1: d+ is high 0: d+ is low table 42. timer n register bit # 15 14 13 12 11 10 9 8 field count... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 table 43. general usb registers register name address (sie1/sie2) r/w usb n control register 0xc08a/0xc0aa r/w table 44. usb n control register bit # 15 14 13 12 11 10 9 8 field port b d+ status port b d? status port a d+ status port a d? status lob loa mode select port b resistors enable read/write r r r r r/w r/w r/w r/w default x x x x 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field port a resistors enable port b force d state port a force d state suspend enable port b sof/eop enable port a sof/eop enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 29 of 102 port b d? status (bit 14) the port b d? status bit is a read only bit that indicates the value of data? on port b. 1: d? is high 0: d? is low port a d+ status (bit 13) the port a d+ status bit is a read only bit that indicates the value of data+ on port a. 1: d+ is high 0: d+ is low port a d? status (bit 12) the port a d? status bit is a read only bit that indicates the value of data? on port a. 1: d? is high 0: d? is low lob (bit 11) the lob bit selects the speed of port b. 1: port b is set to low-speed mode 0: port b is set to full-speed mode loa (bit 10) the loa bit selects the speed of port a. 1: port a is set to low-speed mode 0: port a is set to full-speed mode mode select (bit 9) the mode select bit sets the sie for host or device operation. when set for device operation only one usb port is supported. the active port is selected by the port select bit in the host n count register. 1: host mode 0: device mode port b resistors enable (bit 8) the port b resistors enable bit enables or disables the pull up/pull down resistors on port b. when enabled, the mode select bit and lob bit of this register set the pull up/pull down resistors appropriately. when the mode select is set for host mode, the pull down resistors on the data lines (d+ and d?) are enabled. when the mode select is set for device mode, a single pull up resistor on either d+ or d?, determined by the lob bit, is enabled. see table 45 for details. 1: enable pull up/pull down resistors 0: disable pull up/pull down resistors port a resistors enable (bit 7) the port a resistors enable bit enables or disables the pull up/pull down resistors on port a. when enabled, the mode select bit and loa bit of this register set the pull up/pull down resistors appropriately. when the mode select is set for host mode, the pull down resistors on the data lines (d+ and d?) are enabled. when the mode select is set for device mode, a single pull up resistor on either d+ or d?, determined by the loa bit, is enabled. see table 45 for details. 1: enable pull up/pull down resistors 0: disable pull up/pull down resistors port b force d state (bits [6:5]) the port b force d state field controls the forcing state of the d+ d? data lines for port b. this field forces the state of the port b data lines independent of the port select bit setting. see ta b l e 4 6 for details. port a force d state (bits [4:3]) the port a force d state field controls the forcing state of the d+ d? data lines for port a. this field forces the state of the port a data lines independent of the port select bit setting. see ta b l e 4 6 for details. suspend enable (bit 2) the suspend enable bit enables or disables the suspend feature on both ports. when suspend is enabled the usb transceivers are powered down and cannot transmit or received usb packets but can still monitor for a wakeup condition. 1: enable suspend 0: disable suspend port b sof/eop enable (bit 1) the port b sof/eop enable bit is only applicable in host mode. in device mode, this bit must be written as ?0?. in host mode this bit enables or disables sofs or eops for port b. either sofs or eops are generated depending on the lob bit in the usb n control register when port b is active. 1: enable sofs or eops 0: disable sofs or eops table 45. usb data line pull up and pull down resistors l0a/ l0b mode select port n resistors enable function x x 0 pull up/pull down on d+ and d? disabled x 1 1 pull down on d+ and d? enabled 1 0 1 pull up on usb d? enabled 0 0 1 pull up on usb d+ enabled table 46. port a/b force d state port a/b force d state function msb lsb 0 0 normal operation 1 0 force usb reset, se0 state 0 1 force j-state 1 1 force k-state [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 30 of 102 port a sof/eop enable (bit 0) the port a sof/eop enable bit is only applicable in host mode. in device mode this bit must be written as ?0?. in host mode this bit enables or disables sofs or eops for port a. either sofs or eops are generated depending on the loa bit in the usb n control register when port a is active. 1: enable sofs or eops 0: disable sofs or eops reserved write all reserved bits with ?0?. usb host only registers there are twelve sets of dedicated registers for usb host only o peration. each set consists of two identical registers (unless otherwise noted), one for host port 1 and one for host port 2. these register sets are covered in this section and summarized in ta b l e 4 7 . host n control register [r/w] host 1 control register 0xc080 host 2 control register 0xc0a0 register description the host n control register allows high level usb transaction control. preamble enable (bit 7) the preamble enable bit enables or disables the transmission of a preamble packet before all low-speed packets. set this bit only when communicating with a low-speed device. 1: enable preamble packet 0: disable preamble packet table 47. usb host only register register name address (host 1/host 2) r/w host n control register 0xc080/0xc0a0 r/w host n address register 0xc082/0xc0a2 r/w host n count register 0xc084/0xc0a4 r/w host n endpoint status register 0xc086/0xc0a6 r host n pid register 0xc086/0xc0a6 w host n count result register 0xc088/0xc0a8 r host n device address register 0xc088/0xc0a8 w host n interrupt enable register 0xc08c/0xc0ac r/w host n status register 0xc090/0xc0b0 r/w host n sof/eop count register 0xc092/0xc0b2 r/w host n sof/eop counter register 0xc094/0xc0b4 r host n frame register 0xc096/0xc0b6 r table 48. host n control register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field preamble enable sequence select sync enable iso enable reserved arm enable read/write r/w r/w r/w r/w - - - r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 31 of 102 sequence select (bit 6) the sequence select bit sets the data toggle for the next packet. this bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: send data1 0: send data0 sync enable (bit 5) the sync enable bit synchronizes the transfer with the sof packet in full-speed mode and the eop packet in low-speed mode. 1: the next enabled packet is transferred after the sof or eop packet is transmitted 0: the next enabled packet is transferred as soon as the sie is free iso enable (bit 4) the iso enable bit enables or disables an isochronous trans- action. 1: enable isochronous transaction 0: disable isochronous transaction arm enable (bit 0) the arm enable bit arms an endpoint and starts a transaction. this bit is automatically cleared to ?0? when a transaction is complete. 1: arm endpoint and begin transaction 0: endpoint disarmed reserved write all reserved bits with ?0?. host n address register [r/w] host 1 address register 0xc082 host 2 address register 0xc0a2 register description the host n address register is used as the base pointer into memory space for the current host transactions. address (bits [15:0]) the address field sets the address pointer into internal ram or rom. host n count register [r/w] host 1 count register 0xc084. host 2 count register 0xc0a4. table 49. host n address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 50. host n count register bit # 15 14 13 12 11 10 9 8 field reserved port select reserved count... read/write - r/w - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 32 of 102 register description the host n count register is us ed to hold the number of bytes (packet length) for the current transaction. the maximum packet length is 1023 bytes in iso mode. the host count value is used to determine how many bytes to transmit, or the maximum number of bytes to receive. if the number of received bytes is greater then the host count value then an overflow condition is flagged by the overflow bit in the host n endpoint status register. port select (bit 14) the port select bit selects which of the two active ports is selected and is summarized in ta b l e 5 1 . 1: port 1b or port 2b is enabled 0: port 1a or port 2a is enabled count (bits [9:0]) the count field sets the value for the current transaction data packet length. this value is retained when switching between host and device mode, and back again. reserved write all reserved bits with ?0?. host n endpoint status register [r] host 1 endpoint status register 0xc086 host 2 endpoint status register 0xc0a6 register description the host n endpoint status regist er is a read only register that provides status for the last usb transaction. overflow flag (bit 11) the overflow flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the host n count register. the overflow flag must be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less than the maximum length specified in the host n count register. the underflow flag must be checked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur stall flag (bit 7) the stall flag bit indicates that the peripheral device replied with a stall in the last transaction. 1: device returned stall 0: device did not return stall nak flag (bit 6) the nak flag bit indicates that the peripheral device replied with a nak in the last transaction. 1: device returned nak 0: device did not return nak length exception flag (bit 5) the length exception flag bit indicates that the received data in the data stage of the last transaction does not equal the maximum host count specified in the host n count register. a length exception can either mean an overflow or underflow and the overflow and underflow flags (bits 11 and 10, respectively) must be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur table 51. port select definition port select host/device 1 active port host/device 2 active port 0a a 1b b table 52. host n endpoint status register bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag reserved read/write - - - - r r - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag read/write r r r - r r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 33 of 102 sequence status (bit 3) the sequence status bit indicates the state of the last received data toggle from the device. firmware is responsible for monitoring and handling the sequence status. the sequence bit is only valid if the ack bit is set to ?1?. the sequence bit is set to ?0? when an error is detected in the transaction and the error bit is set. 1: data1 0: data0 timeout flag (bit 2) the timeout flag bit indicates if a timeout condition occurred for the last transaction. a timeout condition can occur when a device either takes too long to respond to a usb host request or takes too long to respond with a handshake. 1: timeout occurred 0: timeout did not occur error flag (bit 1) the error flag bit indicates a transaction failed for any reason other than the following: timeout, receiving a nak, or receiving a stall. overflow and underflow are not considered errors and do not affect this bit. crc5 and crc16 errors result in an error flag along with receiving incorrect packet types. 1: error detected 0: no error detected ack flag (bit 0) the ack flag bit indicates two different conditions depending on the transfer type. for non-isochrono us transfers, this bit repre- sents a transaction ending by receiving or sending an ack packet. for isochronous transfers, this bit represents a successful transaction that is not represented by an ack packet. 1: for non-isochronous transfers, the transaction was acked. for isochronous transfers, the transaction was completed successfully 0: for non-isochronous transfers, the transaction was not acked. for isochronous transfers, the transaction did not complete successfully host n pid register [w] host 1 pid register 0xc086 host 2 pid register 0xc0a6 table 53. host n pid register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field pid select endpoint select read/write w w w w w w w w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 34 of 102 register description the host n pid register is a write only register that provides the pid and endpoint information to the usb sie to be used in the next transaction. pid select (bits [7:4]) the pid select field is defined in ta b l e 5 4 . ack and nak tokens are automatically sent based on settings in the host n control register and do not need to be written in this register. endpoint select (bits [3:0]) the endpoint field allows addressing of up to 16 different endpoints. reserved write all reserved bits with ?0?. host n count result register [r] host 1 count result register 0xc088 host 2 count result register 0xc0a8 register description the host n count result register is a read only register that contains the size difference in bytes between the host count value specified in the host n count register and the last packet received. if an overflow or underflow condition occurs, that is the received packet length differs from the value specified in the host n count register, the length exception flag bit in the host n endpoint status register is set. th e value in this register is only value when the length exception flag bit is set and the error flag bit is not set, both bits are in the host n endpoint status register. result (bits [15:0]) the result field contains the differences in bytes between the received packet and the value specified in the host n count register. if an overflow condition occurs, result [15:10] is set to ?111111?, a 2?s complement value indicating the additional byte count of the received packet. if an underflow condition occurs, result [15:0] indicates the excess bytes count (number of bytes not used). reserved write all reserved bits with ?0?. table 54. pid select definition pid type pid select [7:4] setup 1101 (d hex) in 1001 (9 hex) out 0001 (1 hex) sof 0101 (5 hex) preamble 1100 (c hex) nak 1010 (a hex) stall 1110 (e hex) data0 0011 (3 hex) data1 1011 (b hex) table 55. host n count result register bit # 15 14 13 12 11 10 9 8 field result... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...result read/write r r r r r r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 35 of 102 host n device addr ess register [w] host 1 device address register 0xc088 host 2 device address register 0xc0a8 register description the host n device address register is a write only register that contains the usb device address that the host wants to commu- nicate with. address (bits [6:0]) the address field contains the value of the usb address for the next device that the host is going to communicate with. this value must be written by firmware. reserved write all reserved bits with ?0?. host n interrupt enable register [r/w] host 1 interrupt enable register 0xc08c host 2 interrupt enable register 0xc0ac register description the host n interrupt enable register enables control over host related interrupts. in this register a bit set to ?1? enables the corresponding interrupt while ?0? disables the interrupt. vbus interrupt enable (bit 15) the vbus interrupt enable bit enables or disables the otg vbus interrupt. when enabled this interrupt triggers on both the rising and falling edge of vbus at the 4.4v status (only supported in port 1a). this bit is only available for host 1 and is a reserved bit in host 2. 1: enable vbus interrupt 0: disable vbus interrupt id interrupt enable (bit 14) the id interrupt enable bit enables or disables the otg id interrupt. when enabled this interrupt triggers on both the rising and falling edge of the otg id pin (only supported in port 1a). this bit is only available for host 1 and is a reserved bit in host 2. 1: enable id interrupt 0: disable id interrupt table 56. host n device address register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0 table 57. host n interrupt enable register bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved read/write r/w r/w - - - - r/w - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field port b wake interrupt enable port a wake interrupt enable port b connect change interrupt enable port a connect change interrupt enable reserved done interrupt enable read/write r/w r/w r/w r/w - - - r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 36 of 102 sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit enables or disables the sof/eop timer interrupt 1: enable sof/eop timer interrupt 0: disable sof/eop timer interrupt port b wake interrupt enable (bit 7) the port b wake interrupt enable bit enables or disables the remote wakeup interrupt for port b 1: enable remote wakeup interrupt for port b 0: disable remote wakeup interrupt for port b port a wake interrupt enable (bit 6) the port a wake interrupt enable bit enables or disables the remote wakeup interrupt for port a 1: enable remote wakeup interrupt for port a 0: disable remote wakeup interrupt for port a port b connect change interrupt enable (bit 5) the port b connect change interrupt enable bit enables or disables the port b connect change interrupt on port b. this interrupt triggers when either a device is inserted (se0 state to j state) or a device is removed (j state to se0 state). 1: enable connect change interrupt 0: disable connect change interrupt port a connect change interrupt enable (bit 4) the port a connect change interrupt enable bit enables or disables the connect change interrupt on port a. this interrupt triggers when either a device is inserted (se0 state to j state) or a device is removed (j state to se0 state). 1: enable connect change interrupt 0: disable connect change interrupt done interrupt enable (bit 0) the done interrupt enable bit enables or disables the usb transfer done interrupt. the usb transfer done triggers when either the host responds with an ack, or a device responds with any of the following: ack, nak, stall, or timeout. this interrupt is used for both port a and port b. 1: enable usb transfer done interrupt 0: disable usb transfer done interrupt reserved write all reserved bits with ?0?. host n status register [r/w] host 1 status register 0xc090 host 2 status register 0xc0b0 register description the host n status register prov ides status information for host operation. pending interrupts can be cleared by writing a ?1? to the corresponding bit. this register can be accessed by the hpi interface. vbus interrupt fla g (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of vbus at 4.4v. this bit is only available for host 1 and is a reserved bit in host 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of the otg id pin. this bit is only available for host 1 and is a reserved bit in host 2. 1: interrupt triggered 0: interrupt did not trigger table 58. host n status register bit # 15 14 13 12 11 10 9 8 field vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved read/write r/w r/w - - - - r/w - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field port b wake interrupt flag port a wake interrupt flag port b connect change interrupt flag port a connect change interrupt flag port b se0 status port a se0 status reserved done interrupt flag read/write r/w r/w r/w r/w r/w r/w - r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 37 of 102 sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bit indicates the status of the sof/eop timer interrupt. this bit triggers ?1? when the sof/eop timer expires. 1: interrupt triggered 0: interrupt did not trigger port b wake interrupt flag (bit 7) the port b wake interrupt flag bit indicates remote wakeup on portb. 1: interrupt triggered 0: interrupt did not trigger port a wake interrupt flag (bit 6) the port a wake interrupt flag bit indicates remote wakeup on porta. 1: interrupt triggered 0: interrupt did not trigger port b connect change interrupt flag (bit 5) the port b connect change interrupt flag bit indicates the status of the connect change interrupt on port b. this bit triggers ?1? on either a rising edge or falling edge of a usb reset condition (device inserted or removed). together with the port b se0 status bit, it can be determined whether a device was inserted or removed. 1: interrupt triggered 0: interrupt did not trigger port a connect change interrupt flag (bit 4) the port a connect change interrupt flag bit indicates the status of the connect change interrupt on port a. this bit triggers ?1? on either a rising edge or falling edge of a usb reset condition (device inserted or removed). together with the port a se0 status bit, it can be determined whether a device was inserted or removed. 1: interrupt triggered 0: interrupt did not trigger port b se0 status (bit 3) the port b se0 status bit indicates if port b is in a se0 state or not. together with the port b connect change interrupt flag bit, it can be determined whether a device was inserted (non-se0 condition) or removed (se0 condition). 1: se0 condition 0: non-se0 condition port a se0 status (bit 2) the port a se0 status bit indicates if port a is in a se0 state or not. together with the port a connect change interrupt flag bit, it can be determined whether a device was inserted (non-se0 condition) or removed (se0 condition). 1: se0 condition 0: non-se0 condition done interrupt flag (bit 0) the done interrupt flag bit indicates the status of the usb transfer done interrupt. the usb transfer done triggers when either the host responds with an ack, or a device responds with any of the following: ack, nak, stall, or timeout. this interrupt is used for both port a and port b. 1: interrupt triggered 0: interrupt did not trigger host n sof/eop count register [r/w] host 1 sof/eop count register 0xc092 host 2 sof/eop count register 0xc0b2 register description the host n sof/eop count regi ster contains the sof/eop count value that is loaded into the sof/eop counter. this value is loaded each time the sof/eop counter counts down to zero. the default value set in this register at power up is 0x2ee0 which generates a 1 ms time frame. the sof/eop counter is a down counter decremented at a 12 mhz rate. when this register is read, the value returned is the programmed sof/eop count value. count (bits [13:0]) the count field sets the sof/eop counter duration. reserved write all reserved bits with ?0?. table 59. host n sof/eop count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r/w r/w r/w r/w r/w r/w default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 38 of 102 host n sof/eop counter register [r] host 1 sof/eop counter register 0xc094 host 2 sof/eop counter register 0xc0b4 register description the host n sof/eop counter regist er contains the current value of the sof/eop down counter. this value can be used to determine the time remaining in the current frame. counter (bits [13:0]) the counter field contains the current value of the sof/eop down counter. host n frame register [r] host 1 frame register 0xc096 host 2 frame register 0xc0b6 register description the host n frame register maintains the next frame number to be transmitted (current frame number + 1). this value is updated after each sof transmission. this register resets to 0x0000 after each cpu write to the host n sof/eop count register (host 1: 0xc092 host 2: 0xc0b2). frame (bits [10:0]) the frame field contains the next frame number to be trans- mitted. reserved write all reserved bits with ?0?. table 60. host n sof/eop counter register bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - r r r r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...counter read/write r r r r r r r r default x x x x x x x x table 61. host n frame register bit # 15 14 13 12 11 10 9 8 field reserved frame... read/write - - - - - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 39 of 102 usb device only registers there are eleven sets of usb device only registers. all sets cons ist of at least two registers, one for device port 1 and one f or device port 2. in addition, each device port has eight possible endpoints. this gives each endpoint register set eight registers for e ach device port for a total of sixteen registers per set. the usb device only registers are covered in this section and summarized in table 62 . device n endpoint n control register [r/w] device n endpoint 0 control register [device 1: 0x0200 device 2: 0x0280] device n endpoint 1 control register [device 1: 0x0210 device 2: 0x0290] device n endpoint 2 control register [device 1: 0x0220 device 2: 0x02a0] device n endpoint 3 control register [device 1: 0x0230 device 2: 0x02b0] device n endpoint 4 control register [device 1: 0x0240 device 2: 0x02c0] device n endpoint 5 control register [device 1: 0x0250 device 2: 0x02d0] device n endpoint 6 control register [device 1: 0x0260 device 2: 0x02e0] device n endpoint 7 control register [device 1: 0x0270 device 2: 0x02f0] register description the device n endpoint n control r egister provides control over a single ep in device mode. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n control register. in/out ignore enable (bit 7) the in/out ignore enable bit forces endpoint 0 (ep0) to ignore all in and out requests. set this bit so that ep0 only accepts setup packets at the start of each transfer. clear this bit to accept in/out transactions. this bit only applies to ep0. 1: ignore in/out requests 0: do not ignore in/out requests table 62. usb device only registers register name address (device 1/device 2) r/w device n endpoint n control register 0x02n0 r/w device n endpoint n address register 0x02n2 r/w device n endpoint n count register 0x02n4 r/w device n endpoint n status register 0x02n6 r/w device n endpoint n count result register 0x02n8 r/w device n port select register 0xc084/0xc0a4 r/w device n interrupt enable register 0xc08c/0xc0ac r/w device n address register 0xc08e/0xc0ae r/w device n status register 0xc090/0xcb0 r/w device n frame number register 0xc092/0xc0b2 r device n sof/eop count register 0xc094/0xc0b4 w table 63. device n endpoint n control register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 40 of 102 sequence select (bit 6) the sequence select bit determines whether a data0 or a data1 is sent for the next data toggle. this bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: send a data1 0: send a data0 stall enable (bit 5) the stall enable bit sends a stall in response to the next request (unless it is a setup request, which are always acked). this is a sticky bit and continues to respo nd with stalls until cleared by firmware. 1: send stall 0: do not send stall iso enable (bit 4) the iso enable bit enables and di sables an isochronous trans- action. this bit is only valid for eps 1?7 and has no function for ep0. 1: enable isochronous transaction 0: disable isochronous transaction nak interrupt enable (bit 3) the nak interrupt enable bit enables and disables the gener- ation of an endpoint n interrupt when the device responds to the host with a nak. the endpoint n interrupt enable bit in the device n interrupt enable register must also be set. when a nak is sent to the host, the corresponding ep interrupt flag in the device n status register is set. in addition, the nak flag in the device n endpoint n status register is set. 1: enable nak interrupt 0: disable nak interrupt direction select (bit 2) the direction select bit needs to be set according to the expected direction of the next data stage in the next transaction. if the data stage direction is different from what is set in this bit, it gets naked and either the in exception flag or the out exception flag is set in the device n endpoint n status register. if a setup packet is received and the direction select bit is set incorrectly, the setup is acked and the setup status flag is set (refer to the setup bit of the device n endpoint n status register [r/w] on page 42 for details). 1: out transfer (host to device) 0: in transfer (device to host) enable (bit 1) set the enable bit to allow transfers to the endpoint. if enable is set to ?0? then all usb traffic to this endpoint is ignored. if enable is set ?1? and arm enable (bit 0) is set ?0? then naks are automat- ically returned from this endpoint (except setup packets which are always acked as long as the enable bit is set). 1: enable transfers to an endpoint 0: do not allow transfers to an endpoint arm enable (bit 0) the arm enable bit arms the endpoint to transfer or receive a packet. this bit is cleared to ?0? when a transaction is complete. 1: arm endpoint 0: endpoint disarmed reserved write all reserved bits with ?0?. device n endpoint n address register [r/w] device n endpoint 0 address register [device 1: 0x0202 device 2: 0x0282] device n endpoint 1 address register [device 1: 0x0212 device 2: 0x0292] device n endpoint 2 address register [device 1: 0x0222 device 2: 0x02a2] device n endpoint 3 address register [device 1: 0x0232 device 2: 0x02b2] device n endpoint 4 address register [device 1: 0x0242 device 2: 0x02c2] device n endpoint 5 address register [device 1: 0x0252 device 2: 0x02d2] device n endpoint 6 address register [device 1: 0x0262 device 2: 0x02e2] device n endpoint 7 address register [device 1: 0x0272 device 2: 0x02f2] table 64. device n endpoint n address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 41 of 102 register description the device n endpoint n address register is used as the base pointer into memory space for the current endpoint transaction. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n address register. address (bits [15:0]) the address field sets the base address for the current trans- action on a signal endpoint. device n endpoint n count register [r/w] device n endpoint 0 count register [device 1: 0x0204 device 2: 0x0284] device n endpoint 1 count register [device 1: 0x0214 device 2: 0x0294] device n endpoint 2 count register [device 1: 0x0224 device 2: 0x02a4] device n endpoint 3 count register [device 1: 0x0234 device 2: 0x02b4] device n endpoint 4 count register [device 1: 0x0244 device 2: 0x02c4] device n endpoint 5 count register [device 1: 0x0254 device 2: 0x02d4] device n endpoint 6 count register [device 1: 0x0264 device 2: 0x02e4] device n endpoint 7 count register [device 1: 0x0274 device 2: 0x02f4] register description the device n endpoint n count register designates the maximum packet size that can be received from the host for out transfers for a single endpoint. this register also designates the packet size to be sent to the host in response to the next in token for a single endpoint. the maximum packet length is 1023 bytes in iso mode. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n count register. count (bits [9:0]) the count field sets the current transaction packet length for a single endpoint. reserved write all reserved bits with ?0?. table 65. device n endpoint n count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 42 of 102 device n endpoint n status register [r/w] device n endpoint 0 status register [device 1: 0x0206 device 2: 0x0286] device n endpoint 1 status register [device 1: 0x0216 device 2: 0x0296] device n endpoint 2 status register [device 1: 0x0226 device 2: 0x02a6] device n endpoint 3 status register [device 1: 0x0236 device 2: 0x02b6] device n endpoint 4 status register [device 1: 0x0246 device 2: 0x02c6] device n endpoint 5 status register [device 1: 0x0256 device 2: 0x02d6] device n endpoint 6 status register [device 1: 0x0266 device 2: 0x02e6] device n endpoint 7 status register [d evice 1: 0x0276 device 2: 0x02f6] register description the device n endpoint n status register provides packet status information for the last transaction received or transmitted. this register is updated in hardware and does not need to be cleared by firmware. there are a total of eight endpoints for each of the two ports. all endpoints have the same definition for their device n endpoint n status register. the device n endpoint n status register is a memory based register that must be initialized to 0x0000 before usb device operations are initiated. after initialization, do not write to this register again. overflow flag (bit 11) the overflow flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the device n endpoint n count register. the overflow flag must be checked in response to a length exception signified by the length exception flag set to ?1?. 1: overflow condition occurred 0: overflow condition did not occur underflow flag (bit 10) the underflow flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the device n endpoint n count register. the underflow flag must be checked in response to a length exception signified by the length exception flag set to ?1?. 1: underflow condition occurred 0: underflow condition did not occur out exception flag (bit 9) the out exception flag bit indicates when the device received an out packet when armed for an in. 1: received out when armed for in 0: received in when armed for in in exception flag (bit 8) the in exception flag bit indicates when the device received an in packet when armed for an out. 1: received in when armed for out 0: received out when armed for out stall flag (bit 7) the stall flag bit indicates that a stall packet was sent to the host. 1: stall packet was sent to the host 0: stall packet was not sent nak flag (bit 6) the nak flag bit indicates that a nak packet was sent to the host. 1: nak packet was sent to the host 0: nak packet was not sent length exception flag (bit 5) the length exception flag bit indicates the received data in the data stage of the last transaction does not equal the maximum endpoint count specified in the device n endpoint n count register. a length exception can either mean an overflow or table 66. device n endpoint n status register bit # 15 14 13 12 11 10 9 8 field reserved overflow flag underflow flag out exception flag in exception flag read/write - - - - r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field stall flag nak flag length exception flag setup flag sequence flag timeout flag error flag ack flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 43 of 102 underflow and the overflow and underflow flags (bits 11 and 10 respectively) must be checked to determine which event occurred. 1: an overflow or underflow condition occurred 0: an overflow or underflow condition did not occur setup flag (bit 4) the setup flag bit indicates that a setup packet was received. in device mode setup packets are stored at memory location 0x0300 for device 1 and 0x0308 for device 2. setup packets are always accepted regardless of the direction select and arm enable bit settings as long as the device n ep n control register enable bit is set. 1: setup packet was received 0: setup packet was not received sequence flag (bit 3) the sequence flag bit indicates whether the last data toggle received was a data1 or a data0. this bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: data1 was received 0: data0 was received timeout flag (bit 2) the timeout flag bit indicates whether a timeout condition occurred on the last transaction. on the device side, a timeout can occur if the device sends a data packet in response to an in request but then does not receive a handshake packet in a predetermined time. it can also occur if the device does not receive the data stage of an out transfer in time. 1: timeout occurred 0: timeout condition did not occur error flag (bit 2) the error flag bit is set if a crc5 and crc16 error occurs, or if an incorrect packet type is received. overflow and underflow are not considered errors and do not affect this bit. 1: error occurred 0: error did not occur ack flag (bit 0) the ack flag bit indicates whether the last transaction was acked. 1: ack occurred 0: ack did not occur device n endpoint n count result register [r/w] device n endpoint 0 count result register [device 1: 0x0208 device 2: 0x0288] device n endpoint 1 count result register [device 1: 0x0218 device 2: 0x0298] device n endpoint 2 count result register [device 1: 0x0228 device 2: 0x02a8] device n endpoint 3 count result register [device 1: 0x0238 device 2: 0x02b8] device n endpoint 4 count result register [device 1: 0x0248 device 2: 0x02c8] device n endpoint 5 count result register [device 1: 0x0258 device 2: 0x02d8] device n endpoint 6 count result register [device 1: 0x0268 device 2: 0x02e8] device n endpoint 7 count result register [device 1: 0x0278 device 2: 0x02f8] register description the device n endpoint n count result register contains the size difference in bytes between the endpoint count specified in the device n endpoint n count register and the last packet received. if an overflow or underflow condition occurs, that is, the received packet length differs from the value specified in the device n endpoint n count register, the length exception flag bit in the device n endpoint n status register is set. the value in this register is only valued when the length exception flag bit is set and the error flag bit is not set; both bits are in the device n endpoint n status register. table 67. device n endpoint n count result register bit # 15 14 13 12 11 10 9 8 field result... read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...result read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 44 of 102 the device n endpoint n count result register is a memory-based register that must be initialized to 0x0000 before usb device operations are initiated. after initialization, do not write to this register again. result (bits [15:0]) the result field contains the differences in bytes between the received packet and the value specified in the device n endpoint n count register. if an overflow condition occurs, result [15:10] is set to ?111111?, a 2?s complement value indicating the additional byte count of the received packet. if an underflow condition occurs, result [15:0] indicates the excess bytes count (number of bytes not used). reserved write all reserved bits with ?0?. device n port sele ct register [r/w] device n port select register 0xc084 device n port select register 0xc0a4 register description the device n port select register selects either port a or port b for the static device port. port select (bit 14) the port select bit selects which of the two ports is enabled. 1: port 1b or port 2b is enabled 0: port 1a or port 2a is enabled device n interrupt enable register [r/w] device 1 interrupt enable register 0xc08c device 2 interrupt enable register 0xc0ac register description the device n interrupt enable r egister provides control over device related interrupts including eight different endpoint inter- rupts. vbus interrupt enable (bit 15) the vbus interrupt enable bit enables or disables the otg vbus interrupt. when enabled, this interrupt triggers on both the rising and falling edge of vbus at the 4.4v status (only table 68. device n port select register bit # 15 14 13 12 11 10 9 8 field reserved port select reserved... read/write - r/w - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 table 69. device n interrupt enable register bit # 15 14 13 12 11 10 9 8 field vbus interrupt enable id interrupt enable reserved sof/eop timeout interrupt enable reserved sof/eop interrupt enable reset interrupt enable read/write r/w r/w - - r/w - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 45 of 102 supported in port 1a). this bit is only available for device 1 and is a reserved bit in device 2. 1: enable vbus interrupt 0: disable vbus interrupt id interrupt enable (bit 14) the id interrupt enable bit ena bles or disables the otg id interrupt. when enabled, this interrupt triggers on both the rising and falling edge of the otg id pin (only supported in port 1a). this bit is only available for device 1 and is a reserved bit in device 2. 1: enable id interrupt 0: disable id interrupt sof/eop timeout interrupt enable (bit 11) the sof/eop timeout interrupt e nable bit enables or disables the sof/eop timeout interrupt. when enabled this interrupt triggers when the usb host fails to send a sof or eop packet within the time period specified in the device n sof/eop count register. in addition, the device n frame register counts the number of times the sof/eop timeout interrupt triggers between receiving sof/eops. 1: sof/eop timeout occurred 0: sof/eop timeout did not occur sof/eop interrupt enable (bit 9) the sof/eop interrupt enable bit enables or disables the sof/eop received interrupt. 1: enable sof/eop received interrupt 0: disable sof/eop received interrupt reset interrupt enable (bit 8) the reset interrupt enable bit enables or disables the usb reset detected interrupt 1: enable usb reset detected interrupt 0: disable usb reset detected interrupt ep7 interrupt enable (bit 7) the ep7 interrupt enable bit enables or disables endpoint seven (ep7) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep7 transaction done interrupt 0: disable ep7 transaction done interrupt ep6 interrupt enable (bit 6) the ep6 interrupt enable bit enables or disables endpoint six (ep6) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep6 transaction done interrupt 0: disable ep6 transaction done interrupt ep5 interrupt enable (bit 5) the ep5 interrupt enable bit enables or disables endpoint five (ep5) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep5 transaction done interrupt 0: disable ep5 transaction done interrupt ep4 interrupt enable (bit 4) the ep4 interrupt enable bit enables or disables endpoint four (ep4) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep4 transaction done interrupt 0: disable ep4 transaction done interrupt ep3 interrupt enable (bit 3) the ep3 interrupt enable bit enables or disables endpoint three (ep3) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep3 transaction done interrupt 0: disable ep3 transaction done interrupt ep2 interrupt enable (bit 2) the ep2 interrupt enable bit enables or disables endpoint two (ep2) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep2 transaction done interrupt 0: disable ep2 transaction done interrupt ep1 interrupt enable (bit 1) the ep1 interrupt enable bit enables or disables endpoint one (ep1) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 46 of 102 error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep1 transaction done interrupt 0: disable ep1 transaction done interrupt ep0 interrupt enable (bit 0) the ep0 interrupt enable bit enables or disables endpoint zero (ep0) transaction done interrupt. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied endpoint: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, the nak interrupt enable bit in the device n endpoint control register can also be set so that nak responses trigger this interrupt. 1: enable ep0 transaction done interrupt 0: disable ep0 transaction done interrupt reserved write all reserved bits with ?0?. device n address register [w] device 1 address register 0xc08e device 2 address register 0xc0ae register description the device n address register holds the device address assigned by the host. this register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address. only usb data sent to the address contained in this register gets a respond?all others are ignored. address (bits [6:0]) the address field contains the usb address of the device assigned by the host. reserved write all reserved bits with ?0?. device n status register [r/w] device 1 status register 0xc090 device 2 status register 0xc0b0 table 70. device n address register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved address read/write - w w w w w w w default 0 0 0 0 0 0 0 0 table 71. device n status register bit # 15 14 13 12 11 10 9 8 field vbus inter- rupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag read/write r/w r/w - - - - r/w r/w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 47 of 102 register description the device n status register provides status information for device operation. pending interrupts can be cleared by writing a ?1? to the corresponding bit. this register can be accessed by the hpi interface. vbus interrupt flag (bit 15) the vbus interrupt flag bit indicates the status of the otg vbus interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of vbus at 4.4v. this bit is only available for device 1 and is a reserved bit in device 2. 1: interrupt triggered 0: interrupt did not trigger id interrupt flag (bit 14) the id interrupt flag bit indicates the status of the otg id interrupt (only for port 1a). when enabled this interrupt triggers on both the rising and falling edge of the otg id pin. this bit is only available for device 1 and is a reserved bit in device 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop interrupt flag (bit 9) the sof/eop interrupt flag bit indicates if the sof/eop received interrupt triggered. 1: interrupt triggered 0: interrupt did not trigger reset interrupt flag (bit 8) the reset interrupt flag bit indicates if the usb reset detected interrupt triggered. 1: interrupt triggered 0: interrupt did not trigger ep7 interrupt flag (bit 7) the ep7 interrupt flag bit indicates if the endpoint seven (ep7) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep6 interrupt flag (bit 6) the ep6 interrupt flag bit indicates if the endpoint six (ep6) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep5 interrupt flag (bit 5) the ep5 interrupt flag bit indicates if the endpoint five (ep5) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep4 interrupt flag (bit 4) the ep4 interrupt flag bit indicates if the endpoint four (ep4) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep3 interrupt flag (bit 3) the ep3 interrupt flag bit indicates if the endpoint three (ep3) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 48 of 102 ep2 interrupt flag (bit 2) the ep2 interrupt flag bit indicates if the endpoint two (ep2) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep1 interrupt flag (bit 1) the ep1 interrupt flag bit indicates if the endpoint one (ep1) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger ep0 interrupt flag (bit 0) the ep0 interrupt flag bit indicates if the endpoint zero (ep0) transaction done interrupt triggered. an epx transaction done interrupt triggers when any of the following responses or events occur in a transaction for the device?s supplied ep: send/receive ack, send stall, timeout occurs, in exception error, or out exception error. in addition, if the nak interrupt enable bit in the device n endpoint control register is set, this interrupt also triggers when the device naks host requests. 1: interrupt triggered 0: interrupt did not trigger reserved write all reserved bits with ?0?. device n frame number register [r] device 1 frame number register 0xc092 device 2 frame number register 0xc0b2 register description the device n frame number regist er is a read only register that contains the frame number of the last sof packet received. this register also contains a count of sof/eop timeout occurrences. sof/eop timeout flag (bit 15) the sof/eop timeout flag bit indicates when an sof/eop timeout interrupt occurs. 1: an sof/eop timeout interrupt occurred 0: an sof/eop timeout interrupt did not occur sof/eop timeout interrupt counter (bits [14:12]) the sof/eop timeout interrupt counter field increments by 1 from 0 to 7 for each sof/eop timeout interrupt. this field resets to 0 when a sof/eop is received. this field is only updated when the sof/eop timeout interrupt enable bit in the device n interrupt enable register is set. frame (bits [10:0]) the frame field contains the frame number from the last received sof packet in full-speed mode. this field no function for low-speed mode. if a sof timeout occurs, this field contains the last received frame number. table 72. device n frame number register bit # 15 14 13 12 11 10 9 8 field sof/eop timeout flag sof/eop timeout interrupt counter reserved frame... read/write r r r r - r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...frame read/write r r r r r r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 49 of 102 device n sof/eop count register [w] device 1 sof/eop count register 0xc094 device 2 sof/eop count register 0xc0b4 register description the device n sof/eop count register is written with the time expected between receiving a sof/eop. if the sof/eop counter expires before an sof/eop is received, an sof/eop timeout interrupt can be generated. the sof/eop timeout interrupt enable and sof/eop timeout interrupt flag are located in the device n interrupt enable and status registers respectively. set the sof/eop count slightly greater than the expected sof/eop interval. the sof/eop counter decrements at a 12 mhz rate. therefore, in the case of an expected 1 ms sof/eop interval, the sof/eop count is set slightly greater than 0x2ee0. count (bits [13:0]) the count field contains the current value of the sof/eop down counter. at power up and reset, this value is set to 0x2ee0 and for expected 1 ms sof/eop intervals, this sof/eop count is increased slightly. reserved write all reserved bits with ?0?. otg control registers there is one register dedicated for on-the-go operation. this register is covered in this section and summarized in table 74 . otg control register [0xc098] [r/w] register description the otg control register allows control and monitoring over the otg port on port1a. note that the d pull up and pull down bits override the setting in the usb 0 control register for this port. vbus pull-up enable (bit 13) the vbus pull-up enable bit enables or disables a 500 ohm pull up resistor onto otg vbus. 1: 500 ohm pull up resistor enabled 0: 500 ohm pull up resistor disabled table 73. device n sof/eop count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - r r r r r r default 0 0 1 0 1 1 1 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r r r r r r r r default 1 1 1 0 0 0 0 0 table 74. otg register register name address r/w otg control register c098h r/w table 75. otg control register bit # 15 14 13 12 11 10 9 8 field reserved vbus pull-up enable receive disable charge pump enable vbus discharge enable d+ pull-up enable d? pull-up enable read/write - - r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field d+ pull-down enable d? pull-down enable reserved otg data status id status vbus valid flag read/write r/w r/w - - - r r r default 0 0 0 0 0 x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 50 of 102 receive disable (bit 12) the receive disable bit enables or powers down (disables) the otg receiver section. 1: otg receiver powered down and disabled 0: otg receiver enabled charge pump enable (bit 11) the charge pump enable bit enables or disables the otg vbus charge pump. 1: otg vbus charge pump enabled 0: otg vbus charge pump disabled vbus discharge enable (bit 10) the vbus discharge enable bit enables or disables a 2k ohm discharge pull down resistor onto otg vbus. 1: 2k ohm pull down resistor enabled 0: 2k ohm pull down resistor disabled d+ pull-up enable (bit 9) the d+ pull-up enable bit enables or disables a pull up resistor on the otg d+ data line. 1: otg d+ dataline pull up resistor enabled 0: otg d+ dataline pull up resistor disabled d? pull-up enable (bit 8) the d? pull-up enable bit enables or disables a pull up resistor on the otg d? data line. 1: otg d? dataline pull up resistor enabled 0: otg d? dataline pull up resistor disabled d+ pull-down enable (bit 7) the d+ pull-down enable bit enabl es or disables a pull down resistor on the otg d+ data line. 1: otg d+ dataline pull down resistor enabled 0: otg d+ dataline pull down resistor disabled d? pull-down enable (bit 6) the d? pull-down enable bit enables or disables a pull down resistor on the otg d? data line. 1: otg d? dataline pull down resistor enabled 0: otg d? dataline pull down resistor disabled otg data status (bit 2) the otg data status bit is a read only bit and indicates the ttl logic state of the otg vbus pin. 1: otg vbus is greater then 2.4v 0: otg vbus is less then 0.8v id status (bit 1) the id status bit is a read only bit that indicates the state of the otg id pin on port a. 1: otg id pin is not connected directly to ground (>10k ohm) 0: otg id pin is connected directly ground (< 10 ohm) vbus valid flag (bit 0) the vbus valid flag bit indicates whether otg vbus is greater then 4.4v. after turning on vbus, firmware must wait at least 10 s before this reading this bit. 1: otg vbus is greater then 4.4v 0: otg vbus is less then 4.4v reserved write all reserved bits with ?0?. gpio registers there are seven registers dedicated for gpio operations. these seven registers are covered in this section and summarized in ta b l e 7 6 . table 76. gpio registers register name address r/w gpio control register 0xc006 r/w gpio0 output data register 0xc01e r/w gpio0 input data register 0xc020 r gpio0 direction register 0xc022 r/w gpio1 output data register 0xc024 r/w gpio1 input data register 0xc026 r gpio1 direction register 0xc028 r/w [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 51 of 102 gpio control register [0xc006] [r/w] register description the gpio control register configures the gpio pins for various interface options. it also controls the polarity of the gpio interrupt on irq1 (gpio25) and irq0 (gpio24). write protect enable (bit 15) the write protect enable bit enables or disables the gpio write protect. when write protect is enabled, the gpio mode select [15:8] field is read only until a chip reset. 1: enable write protect 0: disable write protect ud (bit 14) the ud bit routes the host/device 1a port?s transmitter enable status to gpio[30]. this is for use with an external esd protection circuit when needed. 1: route the signal to gpio[30] 0 : do not route the signal to gpio[30] sas enable (bit 11) the sas enable bit, when in spi mode, reroutes the spi port spi_nssi pin to gpio[15] rather then gpio[9] or xd[9] (per sg/sx). 1: reroute spi_nss to gpio[30] 0: leave spi_nss on gpio[9] mode select (bits [10:8]) the mode select field selects how gpio[15:0] and gpio[24:19] are used as defined in table 78 . hss enable (bit 7) the hss enable bit routes hss to gpio[26, 18:16]. if the hss xd enable bit is set, it overrides this bit and hss is routed to xd[15:12]. 1: hss is routed to gpio 0: hss is not routed to gpios. gpio[26, 18:16] are free for other purposes hss xd enable (bit 6) the hss xd enable bit routes hss to xd[15:12] (external memory data bus). this bit overrides the hss enable bit. 1: hss is routed to xd[15:12] 0: hss is not routed to xd[15:12] spi enable (bit 5) the spi enable bit routes spi to gpio[11:8]. if the sas enable bit is set, it overrides the spi enable and routes spi_nssi to gpio15. if the spi xd enable bit is set, it overrides both bits and the spi is routed to xd[11:8] (external memory data bus). 1: spi is routed to gpio[11:8] 0: spi is not routed to gpio[11:8]. gpio[11:8] are free for other purposes spi xd enable (bit 4) the spi xd enable bit routes spi to xd[11:8] (external memory data bus). this bit overrides the spi enable bit. 1: spi is routed to xd[11:8] 0: spi is not routed to xd[11:8] interrupt 1 polarity select (bit 3) the interrupt 1 polarity select bit selects the polarity for irq1. 1: sets irq1 to rising edge 0: sets irq1 to falling edge interrupt 1 enable (bit 2) the interrupt 1 enable bit enables or disables irq1. the gpio bit on the interrupt enable register must also be set in order for this for this interrupt to be enabled. 1: enable irq1 0: disable irq1 table 77. gpio control register bit # 15 14 13 12 11 10 9 8 field write protect enable ud reserved sas enable mode select read/write r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field hss enable hss xd enable spi enable spi xd enable interrupt 1 polarity select interrupt 1 enable interrupt 0 polarity select interrupt 0 enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 78. mode select definition mode select [10:8] gpio configuration 111 reserved 110 scan ? (hw) scan diagnostic. for produc- tion test only. not for normal operation 101 hpi ? host port interface 100 ide ? integrated drive electronics or 011 reserved 010 reserved 001 reserved 000 gpio ? general purpose input output [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 52 of 102 interrupt 0 polarity select (bit 1) the interrupt 0 polarity select bit selects the polarity for irq0. 1: sets irq0 to rising edge 0: sets irq0 to falling edge interrupt 0 enable (bit 0) the interrupt 0 enable bit enables or disables irq0. the gpio bit on the interrupt enable register must also be set in order for this for this interrupt to be enabled. 1: enable irq0 0: disable irq0 reserved write all reserved bits with ?0?. gpio n output data register [r/w] gpio 0 output data register 0xc01e gpio 1 output data register 0xc024 register description the gpio n output data register controls the output data of the gpio pins. the gpio 0 output data register controls gpio15 to gpio0 while the gpio 1 output data register controls gpio31 to gpio16. when read, this register reads back the last data written, not the data on pins configured as inputs (see input data register). data (bits [15:0]) the data field[15:0] writes to the corresponding gpio 15?0 or gpio31?16 pins as output data. gpio n input data register [r] gpio 0 input data register 0xc020 gpio 1 input data register 0xc026 register description the gpio n input data register reads the input data of the gpio pins. the gpio 0 input data r egister reads from gpio15 to gpio0 while the gpio 1 input data register reads from gpio31 to gpio16. data (bits [15:0]) the data field[15:0] contains the voltage values on the corre- sponding gpio15?0 or gpio31?16 input pins. table 79. gpio n output data register bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 field data... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 field ...data read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 80. gpio n input data register bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 field data... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 23/7 22/6 21//5 20/4 19/3 18/2 17/1 16/0 field ...data read/write r r r r r r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 53 of 102 gpio n direction register [r/w] gpio 0 direction register 0xc022 gpio 1 direction register 0xc028 register description the gpio n direction register controls the direction of the gpio data pins (input/output). the gpio 0 direction register controls gpio15 to gpio0 while the gpio 1 direction register controls gpio31 to gpio16. direction select (bits [15:0]) the direction select field[15:0] configures the corresponding gpio15?0 or gpio31?16 pins as either input or output. when any bit of this register is set to ?1?, the corresponding gpio data pin becomes an output. when any bit of this register is set to ?0?, the corresponding gpio data pin becomes an input. ide registers in addition to the standard ide pio port registers, there are four registers dedicated to ide operation. these registers are covered in this section and summarized in table 82 . ide mode register [0xc048] [r/ w] register description the ide mode register allows the selection of ide pio modes 0, 1, 2, 3, or 4. the default setting is zero which means ide pio mode 0. mode select (bits [2:0]) the mode select field sets pio mode 0 to 4 in ide mode. refer to table 84 on page 54 for a definition of this field. table 81. gpio n direction register bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 field direction select... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 field ...direction select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 82. ide registers register name address r/w ide mode register 0xc048 r/w ide start address register 0xc04a r/w ide stop address register 0xc04c r/w ide control register 0xc04e r/w ide pio port registers 0xc050-0xc06f r/w table 83. ide mode register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved mode select read/write - - - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 54 of 102 reserved write all reserved bits with ?0?. ide start address register [0xc04a] [r/w] register description the ide start address register holds the start address for an ide block transfer. this register is byte addressed and ide block transfers are 16-bit words, therefore the lsb of the start address is ignored. block transfers begin at ide start address and end with the final word at ide stop address. when ide start address equals ide stop address, the block transfer moves one word of data. the hardware keeps an internal memory address counter. the two msbs of the addresses are not modified by the address counter. therefore, the ide start address and ide stop address must reside within the same 16k byte block. address (bits [15:0]) the address field sets the start address for an ide block transfer. table 84. mode select definition mode select [2:0] mode 000 ide pio mode 0 001 ide pio mode 1 010 ide pio mode 2 011 ide pio mode 3 100 ide pio mode 4 101 reserved 110 reserved 111 disable ide port operations table 85. ide start address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 55 of 102 ide stop address register [0xc04c] [r/w] register description the ide stop address register holds the stop address for an ide block transfer. this register is byte addressed and ide block transfers are 16-bit words, therefore the lsb of the stop address is ignored. block transfers begin at ide start address and end with the final word at ide stop address. when ide start address equals ide stop address, the block transfer moves one word of data. the hardware keeps an internal memory address counter. the two msbs of the addresses are not modified by the address counter. therefore the ide start address and ide stop address must reside within the same 16k byte block. address (bits [15:0]) the address field sets the stop address for an ide block transfer. ide control register [0xc04e] [r/w] register description the ide control register controls block transfers in ide mode. direction select (bit 3) the direction select bit sets the block mode transfer direction. 1: data is written to the external device 0: data is read from the external device ide interrupt enable (bit 2) the ide interrupt enable bit enables or disables the block transfer done interrupt. when enabled, the done flag is sent to the cpu as cpuide_intr interrupt. when disabled, the cpuide_intr is set low. 1: enable block transfer done interrupt 0: disable block transfer done interrupt done flag (bit 1) the done flag bit is automatically set to ?1? by hardware when a block transfer is complete. the cpu clears this bit by writing a ?0? to it. when ide interrupt enable is set this bit generates the signal for the cpuide_intr interrupt. 1: block transfer is complete 0: clears ide done flag ide enable (bit 0) the ide enable bit starts a block transfer. it is reset to ?0? when the block transfer is complete 1: start block transfer 0: block transfer complete reserved write all reserved bits with ?0?. table 86. ide stop address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 87. ide control register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved direction select ide interrupt enable done flag ide enable read/write - - - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 56 of 102 ide pio port registers [0xc050 - 0xc06f] [r/w] all ide pio port registers [0xc050 - 0xc06f] in table 88 are defined in detail in the information technology-at attachment -4 with packet interface extension (ata/atapi-4) specification, t13/1153d rev 18. the table address column denotes the cy7c67300 register address for the corresponding ata/atapi register. the id e_ncs[1:0] field defines the ata interface cs addressing bits and the ide_a[2:0] field define the ata interface address bits. the combination of ide_ncs and ide_a are the ata interface register address. hss registers there are eight registers dedicated to hss operation. each of these registers are covered in this section and summarized in table 89 . table 88. ide pio port registers address ata/atapi register ide_ncs[1:0] ide_a[2:0] 0xc050 data register ?10? ?000? 0xc052 read: error register write: feature register ?10? ?001? 0xc054 sector count register ?10? ?010? 0xc056 sector number register ?10? ?011? 0xc058 cylinder low register ?10? ?100? 0xc05a cylinder high register ?10? ?101? 0xc05c device/head register ?10? ?110? 0xc05e read: status register write: command register ?10? ?111? 0xc060 not defined ?01? ?000? 0xc062 not defined ?01? ?001? 0xc064 not defined ?01? ?010? 0xc066 not defined ?01? ?011? 0xc068 not defined ?01? ?100? 0xc06a not defined ?01? ?101? 0xc06c read: alternate status register write: device control register ?01? ?110? 0xc06e not defined ?01? ?111? table 89. hss registers register name address r/w hss control register 0xc070 r/w hss baud rate register 0xc072 r/w hss transmit gap register 0xc074 r/w hss data register 0xc076 r/w hss receive address register 0xc078 r/w hss receive length register 0xc07a r/w hss transmit address register 0xc07c r/w hss transmit length register 0xc07e r/w [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 57 of 102 hss control register [0xc070] [r/w] register description the hss control register provides high level status and control over the hss port. hss enable (bit 15) the hss enable bit enables or disables hss operation. 1: enables hss operation 0: disables hss operation rts polarity select (bit 14) the rts polarity select bit selects the polarity of rts. 1: rts is true when low 0: rts is true when high cts polarity select (bit 13) the cts polarity select bit selects the polarity of cts. 1: cts is true when low 0: cts is true when high xoff (bit 12) the xoff bit is a read only bit that indicates if an xoff was received. this bit is automatically cleared when an xon is received. 1: xoff received 0: xon received xoff enable (bit 11) the xoff enable bit enables or disables xon/xoff software handshaking. 1: enable xon/xoff software handshaking 0: disable xon/xoff software handshaking cts enable (bit 10) the cts enable bit enables or disables cts/rts hardware handshaking. 1: enable cts/rts hardware handshaking 0: disable cts/rts hardware handshaking receive interrupt enable (bit 9) the receive interrupt enable bit enables or disables the receive ready and receive packet ready interrupts. 1: enable the receive ready and receive packet ready inter- rupts 0: disable the receive ready and receive packet ready inter- rupts done interrupt enable (bit 8) the done interrupt enable bit enables or disables the transmit done and receive done interrupts. 1: enable the transmit done and receive done interrupts 0: disable the transmit done and receive done interrupts transmit done interrupt flag (bit 7) the transmit done interrupt flag bit indicates the status of the transmit done interrupt. it sets when a block transmit is finished. to clear the interrupt, write a ?1? to this bit. 1: interrupt triggered 0: interrupt did not trigger receive done interrupt flag (bit 6) the receive done interrupt flag bit indicates the status of the receive done interrupt. it sets when a block transmit is finished. to clear the interrupt, write a ?1? to this bit. 1: interrupt triggered 0: interrupt did not trigger one stop bit (bit 5) the one stop bit bit selects between one and two stop bits for transmit byte mode. in receive mode, the number of stop bits may vary and does not need to be fixed. 1: one stop bit 0: two stop bits table 90. hss control register bit # 15 14 13 12 11 10 9 8 field hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive interrupt enable done interrupt enable read/write r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit done interrupt enable receive done interrupt enable one stop bit transmit ready packet mode select receive overflow flag receive packet ready flag receive ready flag read/write r/w r/w r/w r r/w r/w r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 58 of 102 transmit ready (bit 4) the transmit ready bit is a read only bit that indicates if the hss transmit fifo is ready for the cpu to load new data for trans- mission. 1: hss transmit fifo ready for loading 0: hss transmit fifo not ready for loading packet mode select (bit 3) the packet mode select bit se lects between receive packet ready and receive ready as the interrupt source for the rxintr interrupt. 1: selects receive packet ready as the source 0: selects receive ready as the source receive overflow flag (bit 2) the receive overflow flag bit indicates if the receive fifo overflowed when set. this flag can be cleared by writing a ?1? to this bit. 1: overflow occurred 0: overflow did not occur receive packet ready flag (bit 1) the receive packet ready flag bit is a read only bit that indicates if the hss receive fifo is full with eight bytes or not. 1: hss receive fifo is full 0: hss receive fifo is not full receive ready flag (bit 0) the receive ready flag is a read only bit that indicates if the hss receive fifo is empty or not. 1: hss receive fifo is not empty (one or more bytes is reading for reading) 0: hss receive fifo is empty hss baud rate register [0xc072] [r/w] register description the hss baud rate register sets the hss baud rate. at reset, the default value is 0x0017 which sets the baud rate to 2.0 mhz. baud (bits [12:0]) the baud field is the baud rate divisor minus one, in units of 1/48 mhz. therefore the baud rate = 48 mhz/(baud + 1). this puts a constraint on the baud value as follows: (24 ? 1) baud (5000 ? 1) reserved write all reserved bits with ?0?. table 91. hss baud rate register bit # 15 14 13 12 11 10 9 8 field reserved baud... read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...baud read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 1 1 1 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 59 of 102 hss transmit gap register [0xc074] [r/w] register description the hss transmit gap register is only valid in block transmit mode. it allows for a programmable number of stop bits to be inserted, thus overwriting the one stop bit in the hss control register. the default reset value of this register is 0x0009, equiv- alent to two stop bits. transmit gap select (bits [7:0]) the transmit gap select field sets the inactive time between transmitted bytes. the inactive time = (transmit gap select ?7) * bit time. therefore a transmit gap select value of 8 is equal to having one stop bit. reserved write all reserved bits with ?0?. hss data register [0xc076] [r/w] register description the hss data register contains data received on the hss port (not for block receive mode) when read. this receive data is valid when the receive ready bit of the hss control register is set to ?1?. writing to this register initiates a single byte transfer of data. the transmit ready flag in the hss control register must read ?1? before writing to this regist er (this avoids disrupting the previous/current transmission). data (bits [7:0]) the data field contains the data received or to be transmitted on the hss port. reserved write all reserved bits with ?0?. table 92. hss transmit gap register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field transmit gap select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 0 0 1 table 93. hss data register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 60 of 102 hss receive address register [0xc078] [r/w] register description the hss receive address register is used as the base pointer address for the next hss block receive transfer. address (bits [15:0]) the address field sets the base pointer address for the next hss block receive transfer. hss receive counter register [0xc07a] [r/w] register description the hss receive counter regist er designates the block byte length for the next hss receive transfer. load this register with the word count minus one to start the block receive transfer. as each byte is received this register value is decremented. when read, this register indicates the remaining length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved write all reserved bits with ?0?. table 94. hss receive address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 95. hss receive counter register bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 61 of 102 hss transmit address regi ster [0xc07c] [r/w] register description the hss transmit address register is used as the base pointer address for the next hss block transmit transfer. address (bits [15:0]) the address field sets the base pointer address for the next hss block transmit transfer. hss transmit counter register [0xc07e] [r/w] register description the hss transmit counter regist er designates the block byte length for the next hss transmit transfer. load this register with the word count minus one to start the block transmit transfer. as each byte is transmitted this register value is decremented. when read, this register indicates the remaining length of the transfer. counter (bits [9:0]) the counter field value is equal to the word count minus one giving a maximum value of 0x03ff (1023) or 2048 bytes. when the transfer is complete this register returns 0x03ff until reloaded. reserved write all reserved bits with ?0?. table 96. hss transmit address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 97. hss transmit counter register bit # 15 14 13 12 11 10 9 8 field reserved counter... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...counter read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 62 of 102 hpi registers there are five registers dedicated to hpi operation. in addition, there is an hpi status port which can be addressed over hpi. each of these registers is covered in this section and are summa- rized in table 98 . hpi breakpoint register [0x0140] [r] register description the hpi breakpoint register is a special on-chip memory location that the external processor can access using normal hpi memory read/write cycles. this regi ster is read only by the cpu but is read/write by the hpi port. the contents of this register have the same effect as the breakpoint register [0xc014]. this special breakpoint register is used by software debuggers that interface through the hpi port instead of the serial port. when the program counter matches the breakpoint address, the int127 interrupt triggers. to clear this interrupt, write a zero a to this register. address (bits [15:0]) the address field is a 16-bit field containing the breakpoint address. interrupt routing register [0x0142] [r] register description the interrupt routing register allows the hpi port to take over some or all of the sie interrupts that usually go to the on-chip cpu. this register is read only by the cpu but is read/write by the hpi port. by setting the appropriate bit to ?1?, the sie interrupt is routed to the hpi port to become the hpi_intr signal and also readable in the hpi status register. the bits in this register select where the interrupts are routed. the individual interrupt enable is handled in the sie interrupt enable register. vbus to hpi enable (bit 15) the vbus to hpi enable bit routes the otg vbus interrupt to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port table 98. hpi registers register name address r/w hpi breakpoint register 0x0140 r interrupt routing register 0x0142 r sie1msg register 0x0144 w sie2msg register 0x0148 w hpi mailbox register 0xc0c6 r/w table 99. hpi breakpoint register bit # 15 14 13 12 11 10 9 8 field address... read/write r r r r r r r r default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r r r r r r r r default 0 0 0 0 0 0 0 0 table 100. interrupt routing register bit # 15 14 13 12 11 10 9 8 field vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable read/write - - - - - - - - default 0 0 0 1 0 1 0 0 bit # 7 6 5 4 3 2 1 0 field resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable read/write - - - - - - - - default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 63 of 102 id to hpi enable (bit 14) the id to hpi enable bit routes the otg id interrupt to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port sof/eop2 to hpi enable (bit 13) the sof/eop2 to hpi enable bit routes the sof/eop2 interrupt to the hpi port. 1: route signal to hpi port 0 : do not route signal to hpi port sof/eop2 to cpu enable (bit 12) the sof/eop2 to cpu enable bit routes the sof/eop2 interrupt to the on-chip cpu. since the sof/eop2 interrupt can be routed to both the on-chip cpu and the hpi port, the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu sof/eop1 to hpi enable (bit 11) the sof/eop1 to hpi enable bit routes the sof/eop1 interrupt to the hpi port. 1: route signal to hpi port 0: do not route signal to hpi port sof/eop1 to cpu enable (bit 10) the sof/eop1 to cpu enable bit routes the sof/eop1 interrupt to the on-chip cpu. since the sof/eop1 interrupt can be routed to both the on-chip cpu and the hpi port, the firmware must ensure only one of the two (cpu, hpi) resets the interrupt. 1: route signal to cpu 0: do not route signal to cpu reset2 to hpi enable (bit 9) the reset2 to hpi enable bit routes the usb reset interrupt that occurs on device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 1 enable (bit 8) both hpi swap bits (bits 8 and 0) must be set to identical values. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least significant byte goes to hpi_d[7:0]. this is the default setting. by setting to ?11?, the most significant data byte goes to hpi_d[7:0] and the least significant byte goes to hpi_d[15:8]. resume2 to hpi enable (bit 7) the resume2 to hpi enable bit routes the usb resume interrupt that occurs on host 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port resume1 to hpi enable (bit 6) the resume1 to hpi enable bit routes the usb resume interrupt that occurs on host 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done2 to hpi enable (bit 3) the done2 to hpi enable bit routes the done interrupt for host/device 2 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port done1 to hpi enable (bit 2) the done1 to hpi enable bit routes the done interrupt for host/device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port reset1 to hpi enable (bit 1) the reset1 to hpi enable bit routes the usb reset interrupt that occurs on device 1 to the hpi port instead of the on-chip cpu. 1: route signal to hpi port 0: do not route signal to hpi port hpi swap 0 enable (bit 0) both hpi swap bits (bits 8 and 0) must be set to identical values. when set to ?00?, the most significant data byte goes to hpi_d[15:8] and the least significant byte goes to hpi_d[7:0]. this is the default setting. by setting to ?11?, the most significant data byte goes to hpi_d[7:0] and the least significant byte goes to hpi_d[15:8]. [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 64 of 102 siexmsg register [w] sie1msg register 0x0144 sie2msg register 0x0148 register description the siexmsg register allows an interrupt to be generated on the hpi port. any write to this regis ter causes the siexmsg flag in the hpi status port to go high and also causes an interrupt on the hpi_intr pin. the siexmsg flag is automatically cleared when the hpi port reads from this register. data (bits [15:0]) the data field[15:0] simply needs to have any value written to it to cause siexmsg flag in the hpi status port to go high. hpi mailbox register [0xc0c6] [r/w] register description the hpi mailbox register provides a common mailbox between the cy7c67300 and the external host processor. if enabled, the hpi mailbox rx full interrupt triggers when the external host processor writes to this register. when the cy7c67300 reads this register the hpi mailbox rx full interrupt is automatically cleared. if enabled, the hpi mailbox tx empty interrupt triggers when the external host processor reads from this register. the hpi mailbox tx empty interrupt automatically clears when the cy7c67300 writes to this register. in addition, when the cy7c67300 writes to this register, the hpi_intr signal on the hpi port asserts, signaling the external processor that there is data in the mailbox to read. the hpi_intr signal deasserts when the external host processor reads from this register. message (bits [15:0]) the message field contains the message that the host processor wrote to the hpi mailbox register. table 101. siexmsg register bit # 15 14 13 12 11 10 9 8 field data... read/write w w w w w w w w default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field ...data read/write w w w w w w w w default x x x x x x x x table 102. hpi mailbox register bit # 15 14 13 12 11 10 9 8 field message... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...message read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 65 of 102 hpi status port [] [hpi: r] register description the hpi status port provides the external host processor with the mailbox status bits plus several sie status bits. this register is not accessible from the on-chip cpu. the additional sie status bits are provided to aid external device driver firmware devel- opment, and are not recommended for applications that do not have an intimate relationship with the on-chip bios. reading from the hpi status port does not result in a cpu hpi interface memory access cycle. the external host may continu- ously poll this register without degrading the cpu or dma perfor- mance. vbus flag (bit 15) the vbus flag bit is a read only bit that indicates whether otg vbus is greater than 4.4v. after turning on vbus, firmware must wait at least 10 s before this reading this bit. 1: otg vbus is greater than 4.4v 0: otg vbus is less than 4.4v id flag (bit 14) the id flag bit is a read only bit that indicates the state of the otg id pin. sof/eop2 flag (bit 12) the sof/eop2 flag bit is a read only bit that indicates if a sof/eop interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger sof/eop1 flag (bit 10) the sof/eop1 flag bit is a read only bit that indicates if a sof/eop interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger reset2 flag (bit 9) the reset2 flag bit is a read only bit that indicates if a usb reset interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger mailbox in flag (bit 8) the mailbox in flag bit is a read only bit that indicates if a message is ready in the incoming mailbox. this interrupt clears when the on-chip cpu reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger resume2 flag (bit 7) the resume2 flag bit is a read only bit that indicates if a usb resume interrupt occurs on either host/device 2. 1: interrupt triggered 0: interrupt did not trigger resume1 flag (bit 6) the resume1 flag bit is a read only bit that indicates if a usb resume interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger sie2msg (bit 5) the sie2msg flag bit is a read only bit that indicates if the cy7c67300 cpu wrote to the sie2msg register. this bit is cleared on an hpi read. 1: the sie2msg register was written by the cy7c67300 cpu 0: the sie2msg register was not written by the cy7c67300 cpu sie1msg (bit 4) the sie1msg flag bit is a read only bit that indicates if the cy7c67300 cpu wrote to the sie1msg register. this bit is cleared on an hpi read. 1: the sie1msg register was written by the cy7c67300 cpu 0: the sie1msg register was not written by the cy7c67300 cpu done2 flag (bit 3) in host mode the done2 flag bit is a read only bit that indicates if a host packet done interrupt occurs on host 2. in device mode this read only bit indicates if an any of the endpoint interrupts occur on device 2. firmware needs to determine which endpoint interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger table 103. hpi status port bit # 15 14 13 12 11 10 9 8 field vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag read/write r r - r - r r r default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag read/write r r r r r r r r default x x x x x x x x [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 66 of 102 done1 flag (bit 2) in host mode the done 1 flag bit is a read only bit that indicates if a host packet done interrupt occurs on host 1. in device mode this read only bit indicates if an any of the endpoint interrupts occur on device 1. firmware needs to determine which endpoint interrupt occurred. 1: interrupt triggered 0: interrupt did not trigger reset1 flag (bit 1) the reset1 flag bit is a read only bit that indicates if a usb reset interrupt occurs on either host/device 1. 1: interrupt triggered 0: interrupt did not trigger mailbox out flag (bit 0) the mailbox out flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. this interrupt clears when the external host reads from the hpi mailbox register. 1: interrupt triggered 0: interrupt did not trigger spi registers there are twelve registers dedicated to spi operation. each of these registers is covered in this section and summarized in table 104 . table 104. spi registers register name address r/w spi configuration register 0xc0c8 r/w spi control register 0xc0ca r/w spi interrupt enable register 0xc0cc r/w spi status register 0xc0ce r spi interrupt clear register 0xc0d0 w spi crc control register 0xc0d2 r/w spi crc value 0xc0d4 r/w spi data register 0xc0d6 r/w spi transmit address register 0xc0d8 r/w spi transmit count register 0xc0da r/w spi receive address register 0xc0dc r/w spi receive count register 0xc0de r/w [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 67 of 102 spi configuration register [0xc0c8] [r/w] register description the spi configuration register controls the spi port. fields apply to both master and slave mode unless otherwise noted. 3wire enable (bit 15) the 3wire enable bit indicates if the miso and mosi data lines are tied together allowing only half duplex operation. 1: miso and mosi data lines are tied together 0: normal miso and mosi full duplex operation (not tied together) phase select (bit 14) the phase select bit selects advanced or delayed sck phase. this field only applies to master mode. 1: advanced sck phase 0: delayed sck phase sck polarity select (bit 13) this sck polarity select bit selects the polarity of sck. 1: positive sck polarity 0: negative sck polarity scale select (bits [12:9]) the scale select field provides control over the sck frequency, based on 48 mhz. refer to table 106 for a definition of this field. this field only applies to master mode. master active enable (bit 7) the master active enable bit is a read only bit that indicates if the master state machine is active or idle. this field only applies to master mode. 1: master state machine is active 0: master state machine is idle master enable (bit 6) the master enable bit sets the spi interface to master or slave. this bit is only writable when the master active enable bit reads ?0?, otherwise the value does not change. 1: master spi interface 0: slave spi interface ss enable (bit 5) the ss enable bit enables or disables the master ss output. 1: enable master ss output 0: disable master ss output (three state master ss output, for single ss line in slave mode) ss delay select (bits [4:0]) when the ss delay select field is set to ?00000? this indicates manual mode. in manual mode ss is controlled by the ss manual bit of the spi control register. when the ss delay select field is set between ?00001? to ?1 1111?, this value indicates the count in half bit times of auto transfer delay for: ss low to sck active, sck inactive to ss high, ss high time. this field only applies to master mode. table 105. spi configuration register bit # 15 14 13 12 11 10 9 8 field 3wire enable phase select sck polarity select scale select reserved read/write r/w r/w r/w r/w r/w r/w r/w - default 1 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field master active enable master enable ss enable ss delay select read/write r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 1 1 1 table 106. scale select field definition for sck frequency scale select [12:9] sck frequency 0000 12 mhz 0001 8 mhz 0010 6 mhz 0011 4 mhz 0100 3 mhz 0101 2 mhz 0110 1.5 mhz 0111 1 mhz 1000 750 khz 1001 500 khz 1010 375 khz 1011 250 khz 1100 375 khz 1101 250 khz 1110 375 khz 1111 250 khz table 106. scale select fiel d definition for sck frequency scale select [12:9] sck frequency [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 68 of 102 spi control register [0xc0ca] [r/w] register description the spi control register controls the spi port. fields apply to both master and slave mode unless otherwise noted. sck strobe (bit 15) the sck strobe bit starts the sck strobe at the selected frequency and polarity (set in the spi configuration register), but not phase. this bit feature can only be enabled when in master mode and must be during a period of inactivity. this bit is self clearing. 1: sck strobe enable 0: no function fifo init (bit 14) the fifo init bit initializes the fifo and clears the fifo error status bit. this bit is self clearing. 1: fifo init enable 0: no function byte mode (bit 13) the byte mode bit selects between pio (byte mode) and dma (block mode) operation. 1: set pio (byte mode) operation 0: set dma (block mode) operation full duplex (bit 12) the full duplex bit selects between full duplex and half duplex operation. 1: enable full duplex. full duplex is not allowed and does not set if the 3wire enable bit of the spi configuration register is set to ?1? 0: enable half duplex operation ss manual (bit 11) the ss manual bit activates or deactivates ss if the ss delay select field of the spi control register is all zeros and is configured as master interface. this field only applies to master mode. 1: activate ss, master drives ss line asserted low 0: deactivate ss, master drives ss line deasserted high read enable (bit 10) the read enable bit initiates a read phase for a master mode transfer or sets the slave to receive (in slave mode). 1: initiates a read phase for a master transfer or sets a slave to receive. in master mode this bit is sticky and remains set until the read transfer begins. 0: initiates the write phase for slave operation transmit ready (bit 9) the transmit ready bit is a read only bit that indicates if the transmit port is ready to empty and ready to be written. 1: ready for data to be written to the port. the transmit fifo is not full. 0: not ready for data to be written to the port receive data ready (bit 8) the receive data ready bit is a read only bit that indicates if the receive port has data ready. 1: receive port has data ready to read 0: receive port does not have data ready transmit empty (bit 7) the transmit empty bit is a read only bit that indicates if the transmit fifo is empty. 1: transmit fifo is empty 0: transmit fifo is not empty receive full (bit 6) the receive full bit is a read only bit that indicates if the receive fifo is full. 1: receive fifo is full 0: receive fifo is not full transmit bit length (bits [5:3]) the transmit bit length field controls whether a full byte or partial byte is to be transmitted. if transmit bit length is ?000? then a full byte is transmitted. if transmit bit length is ?001? to ?111?, then the value indicates the number of bits that are be transmitted. table 107. spi control register bit # 15 14 13 12 11 10 9 8 field sck strobe fifo init byte mode full duplex ss manual read enable transmit ready receive data ready read/write w w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 1 bit # 7 6 5 4 3 2 1 0 field transmit empty receive full transmit bit length receive bit length read/write r r r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 69 of 102 receive bit length (bits [2:0]) the receive bit length field controls whether a full byte or partial byte is received. if receive bit length is ?000? then a full byte is received. if receive bit length is ?001? to ?111?, then the value indicates the number of bits that are received. spi interrupt enable regi ster [0xc0cc] [r/w] register description the spi interrupt enable regi ster controls the spi port. receive interrupt enable (bit 2) the receive interrupt enable bit enables or disables the byte mode receive interrupt (rxintval). 1: enable byte mode receive interrupt 0: disable byte mode receive interrupt transmit interrupt enable (bit 1) the transmit interrupt enable bit enables or disables the byte mode transmit interrupt (txintval). 1: enables byte mode transmit interrupt 0: disables byte mode transmit interrupt transfer interrupt enable (bit 0) the transfer interrupt enable bit enables or disables the block mode interrupt (xfrblkintval). 1: enables block mode interrupt 0: disables block mode interrupt reserved write all reserved bits with ?0?. spi status register [0xc0ce] [r] register description the spi status register is a read only register that provides status for the spi port. fifo error flag (bit 7) the fifo error flag bit is a read only bit that indicates if a fifo error occurred. when this bit is set to ?1? and the transmit empty bit of the spi control register is set to ?1?, then a tx fifo underflow occurred. similarly, when set with the receive full bit of the spi control register, an rx fifo overflow occured.this bit automatically clears when the spi fifo init enable bit of the spi control register is set. 1: indicates fifo error 0: indicates no fifo error table 108. spi interrupt enable register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive interrupt enable transmit interrupt enable transfer interrupt enable read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 table 109. spi status register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag read/write r - - - - r r r default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 70 of 102 receive interrupt flag (bit 2) the receive interrupt flag is a read only bit that indicates if a byte mode receive interrupt triggered. 1: indicates a byte mode receive interrupt triggered 0: indicates a byte mode receive interrupt did not trigger transmit interrupt flag (bit 1) the transmit interrupt flag is a read only bit that indicates a byte mode transmit interrupt triggered. 1: indicates a byte mode transmit interrupt triggered 0: indicates a byte mode transmit interrupt did not trigger transfer interrupt flag (bit 0) the transfer interrupt flag is a read only bit that indicates a block mode interrupt triggered. 1: indicates a block mode interrupt triggered 0: indicates a block mode interrupt did not trigger spi interrupt clear register [0xc0d0] [w] register description the spi interrupt clear register is a write only register that allows the spi transmit and spi transfer interrupts to be cleared. transmit interrupt clear (bit 1) the transmit interrupt clear bit is a write only bit that clears the byte mode transmit interrupt. this bit is self clearing. 1: clear the byte mode transmit interrupt 0: no function transfer interrupt clear (bit 0) the transfer interrupt clear bit is a write only bit that clears the block mode interrupt. this bit is self clearing. 1: clear the block mode interrupt 0: no function reserved write all reserved bits with ?0?. spi crc control register [0xc0d2] [r/w] register description the spi crc control register provides control over the crc source and polynomial value. crc mode (bits [15:14) the crcmode field selects the crc polynomial as defined in table 112 on page 71 . table 110. spi interrupt clear register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field reserved transmit interrupt clear transfer interrupt clear read/write - - - - - - w w default 0 0 0 0 0 0 0 0 table 111. spi crc control register bit # 15 14 13 12 11 10 9 8 field crc mode crc enable crc clear receive crc one in crc zero in crc reserved... read/write r/w r/w r/w r/w r/w r r - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 71 of 102 crc enable (bit 13) the crc enable bit enables or disables the crc operation. 1: enables crc operation 0: disables crc operation crc clear (bit 12) the crc clear bit clears the crc with a load of all ones. this bit is self clearing and always reads ?0?. 1: clear crc with all ones 0: no function receive crc (bit 11) the receive crc bit determines whether the receive bit stream or the transmit bit stream is used for the crc data input in full duplex mode. this bit is a don?t care in half duplex mode. 1: assigns the receive bit stream 0: assigns the transmit bit stream one in crc (bit 10) the one in crc bit is a read only bit that indicates if the crc value is all zeros or not 1: crc value is not all zeros 0: crc value is all zeros zero in crc (bit 9) the zero in crc bit is a read only bit that indicates if the crc value is all ones or not. 1: crc value is not all ones 0: crc value is all ones reserved write all reserved bits with ?0?. spi crc value register [0xc0d4] [r/w] register description the spi crc value register contains the crc value. crc (bits [15:0]) the crc field contains the spi crc. in crc mode crc7, the crc value is a seven bit value [6:0]. therefore, bits [15:7] are invalid in crc7 mode. table 112. crc mode definition crcmode [15:14] crc polynomial 00 mmc 16 bit: x^16 + x^12 + x^5 + 1(ccitt standard) 01 crc7 7 bit: x^7+ x^3 + 1 10 mst 16 bit: x^16+ x^15 + x^2 + 1 11 reserved, 16 bit polynomial 1 table 113. spi crc value register bit # 15 14 13 12 11 10 9 8 field crc... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 bit # 7 6 5 4 3 2 1 0 field ...crc read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 72 of 102 spi data register [0xc0d6] [r/w] register description the spi data register contains data received on the spi port when read. reading it empties the eight byte receive fifo in pio byte mode. this receive data is valid when the receive interrupt bit of the spi status register is set to ?1? (rxintval triggers) or the receive data ready bit of the spi control register is set to ?1?. writing to this register in pio byte mode initiates a transfer of data, the number of bits defined by transmit bit length field in the spi control register. data (bits [7:0]) the data field contains data received or to be transmitted on the spi port. reserved write all reserved bits with ?0?. spi transmit address register [0xc0d8] [r/w] register description the spi transmit address register is used as the base address for the spi transmit dma. address (bits [15:0]) the address field sets the base address for the spi transmit dma. table 114. spi data register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default x x x x x x x x bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default x x x x x x x x table 115. spi transmit address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 73 of 102 spi transmit count register [0xc0da] [r/w] register description the spi transmit count register designates the block byte length for the spi transmit dma transfer. count (bits [10:0]) the count field sets the count for the spi transmit dma transfer. reserved write all reserved bits with ?0?. spi receive address register [0xc0dc [r/w] register description the spi receive address register is issued as the base address for the spi receive dma. address (bits [15:0]) the address field sets the base address for the spi receive dma. spi receive count register [0xc0de] [r/w] table 116. spi transmit count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 117. spi receive address register bit # 15 14 13 12 11 10 9 8 field address... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 118. spi receive count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 74 of 102 register description the spi receive count register designates the block byte length for the spi receive dma transfer. count (bits [10:0]) the count field sets the count for the spi receive dma transfer. reserved write all reserved bits with ?0?. uart registers there are three registers dedicated to uart operation. each of these registers is covered in this section and summarized in ta b l e 11 9 . uart control register [0xc0e0] [r/w] register description the uart control register enables or disables the uart, allowing gpio28 (uart_txd) and gpio27 (uart_rxd) to be freed up for general use. this register must also be written to set the baud rate, which is based on a 48 mhz clock. scale select (bit 4) the scale select bit acts as a prescaler that divide the baud rate by eight. 1: enable prescaler 0: disable prescaler baud select (bits [3:1]) refer to table 121 for a definition of this field. uart enable (bit 0) the uart enable bit enables or disables the uart. 1: enable uart 0: disable uart. this allows gpio28 and gpio27 to be used for general use. reserved write all reserved bits with ?0?. table 119. uart registers register name address r/w uart control register 0xc0e0 r/w uart status register 0xc0e2 r uart data register 0xc0e4 r/w table 120. uart control register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved scale select baud select uart enable read/write - - - r/w r/w r/w r/w r/w default 0 0 0 0 0 1 1 1 table 121. uart baud select definition baud select [3:1] baud rate w/ div8 = 0 baud rate w/ div8 = 1 000 115.2 kbaud 14.4 kbaud 001 57.6 kbaud 7.2 kbaud 010 38.4 kbaud 4.8 kbaud 011 28.8 kbaud 3.6 kbaud 100 19.2 kbaud 2.4 kbaud 101 14.4 kbaud 1.8 kbaud 110 9.6 kbaud 1.2 kbaud 111 7.2 kbaud 0.9 kbaud [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 75 of 102 uart status register [0xc0e2] [r] register description the uart status register is a read only register that indicates the status of the uart buffer. receive full (bit 1) the receive full bit indicates whet her the receive buffer is full. it can be programmed to interrupt the cpu as interrupt #5 when the buffer is full. this can be done though the uart bit of the interrupt enable register (0xc00 e). this bit is automatically cleared when data is read from the uart data register. 1: receive buffer full 0: receive buffer empty transmit full (bit 0) the transmit full bit indicates whether the transmit buffer is full. it can be programmed to interrupt the cpu as interrupt #4 when the buffer is empty. this can be done though the uart bit of the interrupt enable register (0xc00e). this bit is automatically set to ?1? after data is written by ez-host to the uart data register (to be transmitted). this bit is automatically cleared to ?0? after the data is transmitted. 1: transmit buffer full (transmit busy) 0: transmit buffer is empty and ready for a new byte of data uart data register [0xc0e4] [r/w] register description the uart data register contains data to be transmitted or received from the uart port. data written to this register starts a data transmission and also causes the uart transmit full flag of the uart status register to set. when data received on the uart port is read from this register, the uart receive full flag of the uart status register is cleared. data (bits [7:0]) the data field is where the uart data to be transmitted or received is located. reserved write all reserved bits with ?0?. table 122. uart status register bit # 15 14 13 12 11 10 9 8 field reserved... read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...reserved receive full transmit full read/write - - - - - - r r default 0 0 0 0 0 0 0 0 table 123. uart data register bit # 15 14 13 12 11 10 9 8 field reserved read/write - - - - - - - - default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field data read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 76 of 102 pwm registers there are eleven registers dedicated to pwm operation. each of these registers are covered in this section and summarized in table 124 . pwm control register [0xc0e6] [r/w] register description the pwm control register provides high level control over all four of the pwm channels. pwm enable (bit 15) the pwm enable bit starts and stops pwm operation. 1: start operation 0: stop operation prescale select (bits [11:9]) the prescale select field sets the frequency of all the pwm channels as defined in ta b l e 1 2 6 . table 124. pwm registers register name address r/w pwm control register 0xc0e6 r/w pwm maximum count register 0xc0e8 r/w pwm0 start register 0xc0ea r/w pwm0 stop register 0xc0ec r/w pwm1 start register 0xc0ee r/w pwm1 stop register 0xc0f0 r/w pwm2 start register 0xc0f2 r/w pwm2 stop register 0xc0f4 r/w pwm3 start register 0xc0f6 r/w pwm3 stop register 0xc0f8 r/w pwm cycle count register 0xc0fa r/w table 125. pwm control register bit # 15 14 13 12 11 10 9 8 field pwm enable reserved prescale select mode select read/write r/w - - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field pwm 3 polarity select pwm 2 polarity select pwm 1 polarity select pwm 0 polarity select pwm 3 enable pwm 2 enable pwm 1 enable pwm 0 enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 126. prescaler select definition prescale select [11:9] frequency 000 48.00 mhz 001 24.00 mhz 010 06.00 mhz 011 01.50 mhz 100 375 khz 101 93.80 khz 110 23.40 khz 111 05.90 khz [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 77 of 102 mode select (bit 8) the mode select bit selects between continuous pwm cycling and one shot mode. the default is continuous repeat. 1: enable one shot mode. the mode runs the number of counter cycles set in the pwm cycle count register and then stops. 0: enable continuous mode. runs in continuous mode and starts over after the pw m cycle count is reached. pwm 3 polarity select (bit 7) the pwm 3 polarity select bit selects the polarity for pwm 3. 1: sets the polarity to active high or rising edge pulse 0: sets the polarity to active low pwm 2 polarity select (bit 6) the pwm 2 polarity select bit selects the polarity for pwm 2. 1: sets the polarity to active high or rising edge pulse 0: sets the polarity to active low pwm 1 polarity select (bit 5) the pwm 1 polarity select bit selects the polarity for pwm 1. 1: sets the polarity to active high or rising edge pulse 0: sets the polarity to active low pwm 0 polarity select (bit 4) the pwm 0 polarity select bit selects the polarity for pwm 0. 1: sets the polarity to active high or rising edge pulse 0: sets the polarity to active low pwm 3 enable (bit 3) the pwm 3 enable bit enables or disables pwm 3. 1: enable pwm 3 0: disable pwm 3 pwm 2 enable (bit 2) the pwm 2 enable bit enables or disables pwm 2. 1: enable pwm 2 0: disable pwm 2 pwm 1 enable (bit 1) the pwm 1 enable bit enables or disables pwm 1. 1: enable pwm 1 0: disable pwm 1 pwm 0 enable (bit 0) the pwm 0 enable bit enables or disables pwm 0. 1: enable pwm 0 0: disable pwm 0 pwm maximum count register [0xc0e8] [r/w] register description the pwm maximum count register designates the maximum window for each pulse cycle. each count tick is based on the clock frequency set in the pwm control register. count (bits [9:0]) the count field sets the maximum cycle time. reserved write all reserved bits with ?0?. table 127. pwm maximum count register bit # 15 14 13 12 11 10 9 8 field reserved count... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 78 of 102 pwm n start register [r/w] pwm 0 start register 0xc0ea pwm 1 start register 0xc0ee pwm 2 start register 0xc0f2 pwm 3 start register 0xc0f6 register description the pwm n start register designates where in the window defined by the pwm maximum count register to start the pwm pulse for a supplied channel. address (bits [9:0]) the address field designates when to start the pwm pulse. if this start value is equal to the stop count value then the output stays at false. reserved write all reserved bits with ?0?. pwm n stop register [r/w] pwm 0 stop register 0xc0ec pwm 1 stop register 0xc0f0 pwm 2 stop register 0xc0f4 pwm 3 stop register 0xc0f8 register description the pwm n stop register designates where in the window defined by the pwm maximum count register to stop the pwm pulse for a supplied channel. address (bits [9:0]) the address field designates when to stop the pwm pulse. if the pwm start value is equal to the pwm stop value then the output stays at ?0?. if the pwm stop value is greater then the pwm maximum count value then the output stays at true. reserved write all reserved bits with ?0?. table 128. pwm n start register bit # 15 14 13 12 11 10 9 8 field reserved address... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 table 129. pwm n stop register bit # 15 14 13 12 11 10 9 8 field reserved address... read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...address read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 79 of 102 pwm cycle count register [0xc0fa] [r/w] register description the pwm cycle count register de signates the nu mber of cycles to run when in one shot mode. one shot mode is enabled by setting the mode select bit of the pwm control register to ?1?. count (bits [9:0]) the count field designates the number of cycles (plus one) to run when in one shot mode. for example, cycles = pwm cycle count + 1, therefore for two cycles set pwm cycle count = 1. table 130. pwm cycle count register bit # 15 14 13 12 11 10 9 8 field count... read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 field ...count read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 80 of 102 pin diagram pin descriptions 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gpio24/int/iordy/irq0 gnd a10 xtalout xtalin a11 a12 a13 a14 nxmemsel nxromsel nxramsel vcc a15/clksel gpio31/scl gpio30/sda gpio29/otgid gpio28/tx gpio27/rx gpio26/cts/pwm3 gpio25/irq1 gpio23/nrd/ior gpio22/nwr/iow gpio21/ncs gpio20/a1/cs1 a9 a8 dp1a dm1a avcc a7 dp1b dm1b a6 boostvcc boostgnd vswitch cswitcha cswitchb otgvbus dp2a dm2a a5 a4 agnd dp2b dm2b a3 a2 a1 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd nbel/a0 nbeh a16 a17 a18 gpio0/d0 gpio1/d1 gpio2/d2 gpio3/d3 gpio4/d4 gpio5/d5 vcc gpio6/d6 gpio7/d7 nreset reserved d0 d1 d2 d4 d5 d6 d7 d3 gnd gpio19/a0/cs0 gpio18/a2/rts/pwm2 gpio17/a1/rxd/pwm1 gpio16/a0/txd/pwm0 gpio15/d15/nssi gpio14/d14 gpio13/d13 gpio12/d12 gpio11/d11/mosi gpio10/d10/sck nrd vcc nwr gpio9/d9/nssi gpio8/d8/miso d15/cts d14/rts d13/rxd d12/txd d11/mosi d10/sck d9/nssi d8/miso gnd 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 51 cy7c67300 figure 11. ez-host pin diagram table 131. pin descriptions pin name type description 67 d15/cts io d15: external memory data bus cts: hss cts 68 d14/rts io d14: external memory data bus rts: hss rts 69 d13/rxd io d13: external memory data bus rxd: hss rxd (data is received on this pin) 70 d12/txd io d12: external memory data bus txd: hss txd (data is transmitted from this pin) [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 81 of 102 71 d11/mosi io d11: external memory data bus mosi: spi mosi 72 d10/sck io d10: external memory data bus sck: spi sck 73 d9/nssi io d9: external memory data bus nssi: spi nssi 74 d8/miso io d8: external memory data bus miso: spi miso 76 d7 io external memory data bus 77 d6 io 78 d5 io 79 d4 io 80 d3 io 81 d2 io 82 d1 io 83 d0 io 33 a14 output external memory address bus 32 a13 output 31 a12 output 30 a11 output 27 a10 output 25 a9 output 24 a8 output 20 a7 output 17 a6 output 8 a5 output 7 a4 output 3 a3 output 2 a2 output 1 a1 output 99 nbel/a0 output nbel: low byte enable for 16-bit memories a0: external memory address bit a0 for 0-8 bit memories 98 nbeh output high byte enable for 16-bit memories 64 nwr output external memory write pulse 62 nrd output external memory read pulse 97 a16 output a16: external sram a16 96 a17 output a17: external sram a17 95 a18 output a18: external sram a18 34 nxmemsel output external memory select 0 35 nxromsel output external memory select 1 36 nxramsel output external memory select 2 38 a15/clksel io a15: external sram a15 clksel: sampled directly after reset to determine what crystal or clock source frequency is being used. 12 mhz is required for normal operation so the clksel pin must have a 47k ohm pull up to v cc. after reset this pin functions as a15. 39 gpio31/sck io gpio31: general purpose io sck: i2c eeprom sck 40 gpio30/sda io gpio30: general purpose io sda: i2c eeprom sda table 131. pin descriptions (continued) pin name type description [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 82 of 102 41 gpio29/otgid io gpio29: general purpose io otgid: input for otg id pin. when used as otgid, tie this pin high through an external pull up resistor. assuming v cc = 3.0v, a 10k to 40k resistor must be used. 42 gpio28/tx io gpio28: general purpose io tx: uart tx (data is transmitted from this pin) 43 gpio27/rx io gpio27: general purpose io rx: uart rx (data is received on this pin) 44 gpio26/cts/pwm3 io gpio26: general purpose io cts: hss cts pwm3: pwm channel 3 45 gpio25/irq1 io gpio25: general purpose io irq1: interrupt request 1. see register 0xc006. this pin is also one of two possible gpio wakeup sources. 46 gpio24/int/ iordy/irq0 io gpio24: general purpose io int: hpi int iordy: ide iordy irq0: interrupt request 0. see register 0xc006. this pin is also one of two possible gpio wakeup sources. 47 gpio23/nrd/ior io gpio23: general purpose io nrd: hpi nrd ior: ide ior 48 gpio22/nwr/iow io gpio22: general purpose io nwr: hpi nwr iow: ide iow 49 gpio21/ncs io gpio21: general purpose io ncs: hpi ncs 50 gpio20/a1/cs1 io gpio20: general purpose io a1: hpi a1 cs1: ide cs1 52 gpio19/a0/cs0 io gpio19: general purpose io a0: hpi a0 cs0: ide cs0 53 gpio18/a2/rts/ pwm2 io gpio18: general purpose io a2: ide a2 rts: hss rts pwm2: pwm channel 2 54 gpio17/a1/rxd/ pwm1 io gpio17: general purpose io a1: ide a1 rxd: hss rxd (data is received on this pin) pwm1: pwm channel 1 55 gpio16/a0/txd/ pwm0 io gpio16: general purpose io a0: ide a0 txd: hss txd (data is transmitted from this pin) pwm0: pwm channel 0 56 gpio15/d15/nssi io gpio15: general purpose io d15: d15 for hpi or ide nssi: spi nssi 57 gpio14/d14 io gpio14: general purpose io d14: d14 for hpi or ide 58 gpio13/d13 io gpio13: general purpose io d13: d13 for hpi or ide 59 gpio12/d12 io gpio12: general purpose io d12: d12 for hpi or ide table 131. pin descriptions (continued) pin name type description [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 83 of 102 60 gpio11/d11/mosi io gpio11: general purpose io d11: d11 for hpi or ide mosi: spi mosi 61 gpio10/d10/sck io gpio10: general purpose io d10: d10 for hpi or ide sck: spi sck 65 gpio9/d9/nssi io gpio9: general purpose io d9: d9 for hpi or ide nssi: spi nssi 66 gpio8/d8/miso io gpio8: general purpose io d8: d8 for hpi or ide miso: spi miso 86 gpio7/d7 io gpio7: general purpose io d7: d7 for hpi or ide 87 gpio6/d6 io gpio6: general purpose io d6: d6 for hpi or ide 89 gpio5/d5 io gpio5: general purpose io d5: d5 for hpi or ide 90 gpio4/d4 io gpio4: general purpose io d4: d4 for hpi or ide 91 gpio3/d3 io gpio3: general purpose io d3: d3 for hpi or ide 92 gpio2/d2 io gpio2: general purpose io d2: d2 for hpi or ide 93 gpio1/d1 io gpio1: general purpose io d1: d1 for hpi or ide 94 gpio0/d0 io gpio0: general purpose io d0: d0 for hpi or ide 22 dm1a io usb port 1a d? 23 dp1a io usb port 1a d+ 18 dm1b io usb port 1b d? 19 dp1b io usb port 1b d+ 9 dm2a io usb port 2a d? 10 dp2a io usb port 2a d+ 4 dm2b io usb port 2b d? 5 dp2b io usb port 2b d+ 29 xtalin input crystal input or direct clock input 28 xtalout output crystal output . leave floating if direct clock source is used. 85 nreset input reset 84 reserved - tie to gnd for normal operation . 16 boostv cc power booster power input : 2.7v to 3.6v 14 vswitch analog output booster switching output 15 boostgnd ground booster ground 11 otgvbus analog io usb otg vbus 13 cswitcha analog charge pump capacitor 12 cswitchb analog charge pump capacitor 21 av cc power usb power 6 agnd ground usb ground 37, 63, 88 v cc power main v cc 26, 51, 75, 100 gnd ground main ground table 131. pin descriptions (continued) pin name type description [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 84 of 102 absolute maximum ratings this section lists the absolute maximum ratings. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for extended periods can affect device operation and reliability. storage temperature .................................. ?40c to +125c ambient temperature with power supplied.. ?40c to +85c supply voltage to ground potential..................0.0v to +3.6v dc input voltage to any general purpose input pin..... 5.5v dc voltage applied to xtalin ............. ?0.5v to v cc + 0.5v static discharge voltage.......................................... > 2000v max output current, per io .......................................... 4 ma operating conditions t a (ambient temperature under bias) ......... ?40c to +85c supply voltage (v cc , av cc ) ...........................+3.0v to +3.6v supply voltage (boostv cc ) [7] .........................+2.7v to +3.6v ground voltage.................................................................. 0v f osc (oscillator or crystal frequency).... 12 mhz 500 ppm ................................................................... parallel resonant crystal requirements (xtalin, xtalout) dc characteristics notes 7. the on-chip voltage booster circuit boosts boostv cc to provide a nominal 3.3v v cc supply. 8. all tests were conducted with charge pump off. table 132. crystal requirements crystal requirements (xtalin, xtalout) min typical max unit parallel resonant frequency 12 mhz frequency stability ?500 +500 ppm load capacitance 20 33 pf driver level 500 w startup time 5ms mode of vibration: fundamental table 133. dc characteristics [8] parameter description conditions min typ. max unit v cc , av cc supply voltage 3.0 3.3 3.6 v boosv cc supply voltage 2.7 3.6 v v ih input high voltage 2.0 5.5 v v il input low voltage 0.8 v i i input leakage current 0< v in < v cc ?10.0 +10.0 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ?4 ma 0.4 v i oh output current high 10 20 ma i ol output current low 10 20 ma c in input pin capacitance except d+/d? 10 pf d+/d? 15 pf v hys hysteresis on nreset pin 250 mv i cc [9, 10] supply current 4 transceivers powered 80 100 ma i ccb [9, 10] supply current with booster enabled 4 transceivers powered 135 180 ma [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 85 of 102 usb transceiver usb 2.0 certified in full- and low-speed modes. i sleep sleep current usb peripheral: includes 1.5k internal pull up 210 500 a without 1.5k internal pull up 5 30 a i sleepb sleep current with booster enabled usb peripheral: includes 1.5k internal pull up 190 500 a without 1.5k internal pull up 5 30 a table 133. dc characteristics (continued) [8] parameter description conditions min typ. max unit notes 9. i cc and i ccb values are the same regardless of usb host or peripheral configuration. 10. there is no appreciable difference in i cc and i ccb values when only two transceivers are powered. table 134. dc characteristics: charge pump parameter description conditions min typ. max unit v a_vbus_out regulated otgvbus voltage 8 ma< i load < 10 ma 4.4 5.25 v t a_vbus_rise v bus rise time i load = 10 ma 100 ms i a_vbus_out maximum load current 8 10 ma c drd_vbus outvbus bypass capacitance 4.4v< v bus < 5.25v 1.0 6.5 pf v a_vbus_lkg otgvbus leakage voltage otgvbus not driven 200 mv v drd_data_lkg dataline leakage voltage 342 mv i charge charge pump current draw i load = 8 ma 20 20 ma i load = 0 ma 0 1 ma i chargeb charge pump current draw with booster active i load = 8 ma 30 45 ma i load = 0 ma 0 5 ma i b_dschg_in b-device (srp capable) discharge current 0v< v bus < 5.25v 8 ma v a_vbus_valid a-device vbus valid 4.4 v v a_sess_valid a-device session valid 0.8 2.0 v v b_sess_valid b-device session valid 0.8 4.0 v v a_sess_end b-device session end 0.2 0.8 v e efficiency when loaded i load = 8 ma, v cc = 3.3v 75 % r pd data line pull down 14.25 24.8 r a_bus_in a-device v bus input impedance to gnd v bus is not being driven 40 100 k r b_srp_up b-device v bus srp pull up pull up voltage = 3.0v 281 r b_srp_dwn b-device v bus srp pull down 656 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 86 of 102 ac timing characteristics reset timing clock timing notes 11. clock is 12 mhz nominal. 12. v xinh is required to be 3.0 v to obtain an internal 50/50 duty cycle clock. table 135. reset timing parameters parameter description min typical max unit t reset nreset pulse width 16 clocks [11] t ioact nreset high to nrd or nwrx active 200 s nreset nrd or nwrl or nwrh t reset t ioact reset timing table 136. clock timing parameters parameter description min typical max unit f clk clock frequency 12.0 mhz v xinh [12] clock input high (xtalout left floating) 1.5 3.0 3.6 v t clk clock period 83.17 83.33 83.5 ns t high clock high time 36 44 ns t low clock low time 36 44 ns t rise clock rise time 5.0 ns t fall clock fall time 5.0 ns duty cycle 45 55 % xtalin clock timing t rise t fall t high t clk t low [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 87 of 102 sram read cycle [15] notes 13. 0 wait state cycle. 14. t ac external sram access time = 12 ns for zero and one wait states. t he external sram access time = 12 ns + (n ? 1)*t for wait sta tes = n, n > 1, t = 48 mhz clock period. 15. read timing is applicable for nxmemsel, nxramsel, and nxromsel. table 137. sram read cycle parameters parameter description min typical max unit t cr cs low to rd low 1 ns t rdh rd high to data hold 0 ns t cdh cs high to data hold 0 ns t rpw [13] rd low time 38 45 ns t ar rd low to address valid 0 ns t ac [14] ram access to data valid 12 ns address cs rd din t ar t rpw data valid t cr t ac t rdh t cdh [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 88 of 102 sram write cycle [17] notes 16. t wpw the write pulse width = 18.8 ns min. for zero and one wait states. the write pulse = 18.8 ns + (n ? 1)*t for wait states = n, n > 1, t = 48 mhz clock period. 17. write timing is applicable for nxmemsel, nxramsel and nxromsel. table 138. sram write cycle parameters parameter description min typical max unit t aw write address valid to we low 7 ns t csw cs low to we low 7 ns t dw data valid to we high 15 ns t wpw [16] we pulse width 15 ns t dh data hold from we high 4.5 ns t wc we high to cs high 13 ns address cs we dout t aw t csw t wpw t dw t wc t dh data valid [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 89 of 102 i2c eeprom timing-serial io table 139. i2c eeprom timing parameters parameter description min typical max unit f scl clock frequency 400 khz t low clock pulse width low 1300 ns t high clock pulse width high 600 ns t aa clock low to data out valid 900 ns t buf bus idle before new transmission 1300 ns t hd.sta start hold time 600 ns t su.sta start setup time 600 ns t hd.dat data in hold time 0 ns t su.dat data in setup time 100 ns t r input rise time 300 ns t f input fall time 300 ns t su.sto stop setup time 600 ns t dh data out hold time 0 ns scl t low t high t r t hd.dat t aa t dh sda in sda out t su.sta t hd.sta t f t su.dat t buf t su.sto [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 90 of 102 hpi (host port interface) write cycle timing notes 18. t = system clock period = 1/48 mhz. table 140. hpi write cycle timing parameters parameter description min typical max unit t asu address setup ?1 ns t ah address hold ?1 ns t cssu chip select setup ?1 ns t csh chip select hold ?1 ns t dsu data setup 6 ns t wdh write data hold 2 ns t wp write pulse width 2 t [18] t cyc write cycle time 6 t [18] ncs nrd nwr addr [1:0] dout [15:0] t asu t wp t ah t cssu t csh t cyc t dsu t wdh [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 91 of 102 hpi (host port interface) read cycle timing table 141. hpi read cycle timing parameters parameter description min typical max unit t asu address setup ?1 ns t ah address hold ?1 ns t cssu chip select setup ?1 ns t csh chip select hold ?1 ns t acc data access time, from hpi_nrd falling 1 t [18] t rdh read data hold, relative to the earlier of hpi_nrd rising or hpi_ncs rising 1.5 7 ns t rp read pulse width 2 t [18] t cyc read cycle time 6 t [18] t asu t rp t ah t cssu t csh t cyc t rdh t acc t rdh ncs nrd nwr addr [1:0] din [15:0] [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 92 of 102 ide timing the ide interface supports pio mode 0-4 as specified in the in formation technology-at attachment?4 with packet interface extens ion (ata/atapi-4) specification, t13/1153d rev 18. hss byte mode transmit qt_clk, cpu_a, cpuhss_cs, cpu_wr are internal signals, includ ed in the diagram to illustrate the relationship between cpu opera - tions and hss port operations. bit 0 is lsb of data byte. data bits are high true: hss_txd high = data bit value ?1?. bt = bit time = 1/baud rate. hss block mode transmit block mode transmit timing is similar to byte mode, except the stop bit time is controlled by the hss_gap value. the block mode stop bit time, t gap = (hss_gap ? 9) bt, where bt is the bit time, and hss_gap is the content of the hss transmit gap register [0xc074]. the default t gap is 2 bt. bt = bit time = 1/baud rate. hss byte and block mode receive receive data arrives asynchronously relative to the internal clock. incoming data bit rate may deviate from the programmed baud rate clock by as much as 5% (with hss_rate value of 23 or higher). byte mode received bytes are buffered in a fifo. the fifo not empty condition becomes the rxrdy flag. block mode received bytes are written directly to the memory system. bit 0 is lsb of data byte. data bits are high true: hss_rxd high = data bit value ?1?. bt = bit time = 1/baud rate. cpu may start another byte transmit right after txrdy goes high start of last data bit to txrdy high: 0 min, 4 t max. (t is qt_clk period) txrdy low to start bit delay: 0 min, bt max when starting from idel. for back to back transmit, new start bit begins immediately following previous stop bit. (bt = bit period) bt bt start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 qt_clk cpu_a[2:0] cpuhss_cs cpu_wr txrdy flag hss_txd byte transmit triggered by a cpu write to the hss_txdata register stop bit start bit programmable 1 or 2 stop bits. 1 stop bit shown. hss_txd t gap bt bt +/- 5% start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit hss_rxd bt +/- 5% 10 bt +/- 5% received byte added to receive fifo during the final data bit time [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 93 of 102 hardware cts/rts handshake t ctssetup : hss_cts setup time before hss_rts = 1.5t min. t ctshold : hss_cts hold time after start bit = 0 ns min. t = 1/48 mhz. when rts/cts hardware handshake is enabled, transmission can be help off by deasserting hss_cts at least 1.5t before hss_rts. transmission resumes w hen hss_cts returns high . hss_cts must remain high until start bit. hss_rts is deasserted in the third data bit time. an application may choose to hold hss_cts until hss_rts is deasserted, which always occurs after the start bit. register summary tctssetup tctssetup start of transmission delayed until hss_cts goes high start of transmission not delayed by hss_cts tctshold tctshold hss_rts hss_cts hss_txd table 142. register summary r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low r 0x0140 hpi breakpoint address... 0000 0000 ...address 0000 0000 r 0x0142 interrupt routing vbus to hpi enable id to hpi enable sof/eop2 to hpi enable sof/eop2 to cpu enable sof/eop1 to hpi enable sof/eop1 to cpu enable reset2 to hpi enable hpi swap 1 enable 0001 0100 resume2 to hpi enable resume1 to hpi enable reserved done2 to hpi enable done1 to hpi enable reset1 to hpi enable hpi swap 0 enable 0000 0000 w 1: 0x0144 2: 0x0148 siexmsg data... xxxx xxxx ...data xxxx xxxx r/w 0x02n0 device n endpoint n control reserved xxxx xxxx in/out ignore enable sequence select stall enable iso enable nak interrupt enable direction select enable arm enable xxxx xxxx r/w 0x02n2 device n endpoint n address address... xxxx xxxx ...address xxxx xxxx r.w 0x02n4 device n endpoint n count reserved count... xxxx xxxx ...count xxxx xxxx r/w 0x02n6 device n endpoint n status reserved overflow flag underflow flag out exception flag in exception flag xxxx xxxx stall flag nak flag length exception flag setup flag sequence status timeout flag error flag ack flag xxxx xxxx r/w 0x02n8 device n endpoint n count result result... xxxx xxxx ...result xxxx xxxx r 0xc000 cpu flags reserved... 0000 0000 ...reserved global inter- rupt enable negative flag overflow flag carry flag zero flag 000x xxxx r/w 0xc002 bank address... 0000 0001 ...address reserved 000x xxxx r 0xc004 hardware revision revision... xxxx xxxx ...revision xxxx xxxx r/w 0xc006 gpio control write protect enable ud reserved sas enable mode select 0000 0000 hss enable hss xd enable spi enable spi xd enable interrupt 1 polarity select interrupt 1 enable interrupt 0 polarity select interrupt 0 enable 0000 0000 r/w 0xc008 cpu speed reserved... 0000 0000 .reserved cpu speed 0000 1111 r/w 0xc00a power control host/device 2b wake enable host/device 2a wake enable host/device 1b wake enable host/device 1a wake enable otg wake enable reserved hss wake enable spi wake enable 0000 0000 hpi wake enable reserved gpi wake enable reserved boost 3v ok sleep enable halt enable 0000 0000 [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 94 of 102 r/w 0xc00c watchdog timer reserved... 0000 0000 ...reserved timeout flag period select lock enable wdt enable reset strobe 0000 0000 r/w 0xc00e interrupt enable reserved otg interrupt enable spi interrupt enable reserved host/device 2 interrupt enable host/device 1 interrupt enable 0000 0000 hss interrupt enable in mailbox interrupt enable out mailbox interrupt enable reserved uart interrupt enable gpio interrupt enable timer 1 interrupt enable timer 0 interrupt enable 0001 0000 r/w 0xc098 otg control reserved vbus pull-up enable receive disable charge pump enable vbus discharge enable d+ pull-up enable d? pull-up enable 0000 0000 d+ pulldown enable d? pull-down enable reserved otg data status id status vbus valid flag 0000 0xxx r/w 0: 0xc010 1: 0xc012 timer n count... 1111 1111 ...count 1111 1111 r/w 0xc014 breakpoint address... 0000 0000 ...address 0000 0000 r/w 1: 0xc018 2: 0xc01a extended page n map address... 0000 0000 ...address 0000 0000 r/w 0: 0xc01e 1: 0xc024 gpio n output data data... 0000 0000 ...data 0000 0000 r0: 0xc020 1: 0xc026 gpio n input data data... 0000 0000 ...data 0000 0000 r/w 0: 0xc022 1: 0xc028 gpio n direction direction select... 0000 0000 ...direction select 0000 0000 r/w 0xc038 upper address enable reserved xxxx xxxx reserved upper address enable reserved xxxx 0xxx r/w 0xc03a external memory control reserved xram merge enable xrom merge enable xmem width select xmem wait select xxxx xxxx xrom width select xrom wait select xram width select xram wait select xxxx xxxx r/w 0xc03c usb diagnostic port 2b diagnostic enable port 2a diagnostic enable port 1b diagnostic enable port 1a diagnostic enable reserved... 0000 0000 ...reserved pull-down enable ls pull-up enable fs pull-up enable reserved force select 0000 0000 w 0xc03e memory diagnostic reserved memory arbitration select 0000 0000 reserved monitor enable 0000 0000 r/w 0xc048 ide mode reserved... 0000 0000 ...reserved reserved mode select 0000 0000 r/w 0xc04a ide start address address... 0000 0000 ... address 0000 0000 r/w 0xc04c ide stop address address... 0000 0000 ...address 0000 0000 r/w 0xc04e ide control reserved... 0000 0000 ...reserved direction select ide interrupt enable done flag ide enable 0000 0000 - 0xc050-0 xc06e ide pio port r/w 0xc070 hss control hss enable rts polarity select cts polarity select xoff xoff enable cts enable receive interrupt enable done interrupt enable 0000 0000 transmit done interrupt flag receive done interrupt flag one stop bit transmit ready packet mode select receive overflow flag receive pack- et ready flag receive ready flag 0000 0000 r/w 0xc072 hss baud rate reserved hss baud... 0000 0000 ...baud 0001 0111 r/w 0xc074 hss transmit gap reserved 0000 0000 transmit gap select 0000 1001 r/w 0xc076 hss data reserved xxxx xxxx data xxxx xxxx r/w 0xc078 hss receive address address... 0000 0000 ...address 0000 0000 r/w 0xc07a hss receive counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc07c hss transmit address address.. 0000 0000 ...address 0000 0000 table 142. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 95 of 102 r/w 0xc07e hss transmit counter reserved counter... 0000 0000 ...counter 0000 0000 r/w 0xc080 0xc0a0 host n control reserved 0000 0000 preamble enable sequence select sync enable iso enable reserved arm enable 0000 0000 r/w 0xc082 0xc0a2 host n address address... 0000 0000 ...address 0000 0000 r/w 0xc084 0xc0a4 host n count reserved port select reserved count... 0000 0000 ...count 0000 0000 r/w 0xc084 0xc0a4 device n port select reserved port select reserved... 0000 0000 ...reserved 0000 0000 r 0xc086 0xc0a6 host n pid reserved overflow flag underflow flag reserved 0000 0000 stall flag nak flag length exception flag reserved sequence status timeout flag error flag ack flag 0000 0000 w 0xc086 0xc0a4 host n ep status reserved 0000 0000 pid select endpoint select 0000 0000 r 0xc088 0xc0a8 host n count result result... 0000 0000 ...result 0000 0000 w 0xc088 0xc0a8 host n device address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc08a 0xc0aa usb n control port b d+ status port b d? status port a d+ status port a d? status lob loa mode select port b resis- tors enable xxxx 0000 port a resistors enable port b force d+/- state port a force d state suspend enable port b sof/eop enable port a sof/eop enable 0000 0000 r/w 0xc08c host 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 port b wake interrupt enable port a wake interrupt enable port b connect change interrupt en- able port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 r/w 0xc08c device 1 interrupt enable vbus interrupt enable id interrupt enable reserved sof/eop timeout in- terrupt en- able reserved sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc08e 0xc0ae device n address reserved... 0000 0000 ...reserved address 0000 0000 r/w 0xc090 host 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reserved xxxx xxxx port b wake interrupt flag port a wake interrupt flag port b connect change interrupt flag port a con- nect change interrupt flag port b se0 status port a se0 status reserved done interrupt flag xxxx xxxx r/w 0xc090 device 1 status vbus interrupt flag id interrupt flag reserved sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc092 0xc0b2 host n sof/eop count reserved count... 0010 1110 ...count 1110 0000 r 0xc092 0xc0b2 device n frame number sof/eop timeout flag sof/eop timeout interrupt count reserved frame... 0000 0000 ...frame 0000 0000 r 0xc094 0xc0b4 host n sof/eop counter reserved counter... xxxx xxxx ...counter xxxx xxxx w 0xc094 0xc0b4 device n sof/eop count reserved count... 0010 1110 ...count 1110 0000 r 0xc096 0xc0b6 host n frame reserved frame... 0000 0000 ...frame 0000 0000 r/w 0xc0ac host 2 interrupt enable reserved sof/eop interrupt enable reserved 0000 0000 port b wake interrupt enable port a wake interrupt enable port b connect change interrupt enable port a con- nect change interrupt enable reserved done interrupt enable 0000 0000 table 142. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 96 of 102 r/w 0xc0ac device 2 interrupt enable reserved sof/eop timeout interrupt enable wake interrupt enable sof/eop interrupt enable reset interrupt enable 0000 0000 ep7 interrupt enable ep6 interrupt enable ep5 interrupt enable ep4 interrupt enable ep3 interrupt enable ep2 interrupt enable ep1 interrupt enable ep0 interrupt enable 0000 0000 r/w 0xc0b0 host 2 status reserved sof/eop interrupt flag reserved xxxx xxxx port b wake interrupt flag port a wake interrupt flag port b connect change interrupt flag port a connect change interrupt flag port b se0 status port a se0 status reserved done interrupt flag xxxx xxxx r/w 0xc0b0 device 2 status reserved sof/eop timeout interrupt enable wake interrupt flag sof/eop interrupt flag reset interrupt flag xxxx xxxx ep7 interrupt flag ep6 interrupt flag ep5 interrupt flag ep4 interrupt flag ep3 interrupt flag ep2 interrupt flag ep1 interrupt flag ep0 interrupt flag xxxx xxxx r/w 0xc0c6 hpi mailbox message... 0000 0000 ...message 0000 0000 r/w 0xc0c8 spi configuration 3wire enable phase select sck polarity select scale select reserved 1000 0000 master active enable master enable ss enable ss delay select 0001 1111 r/w 0xc0ca spi control sck strobe fifo init byte mode fullduplex ss manual read enable transmit ready receive data ready 0000 0001 transmit empty receive full transmit bit length receive bit length 1000 0000 r/w 0xc0cc spi interrupt enable reserved... 0000 0000 ...reserved receive inter- rupt enable transmit inter- rupt enable transfer inter- rupt enable 0000 0000 r 0xc0ce spi status reserved... 0000 0000 fifo error flag reserved receive interrupt flag transmit interrupt flag transfer interrupt flag 0000 0000 w 0xc0d0 spi interrupt clear reserved... 0000 0000 ...reserved transmit interrupt clear transmit interrupt clear 0000 0000 r/w 0xc0d2 spi crc control crc mode crc enable crc clear receive crc one in crc zero in crc reserved... 0000 0000 ...reserved 0000 0000 r/w 0xc0d4 spi crc value crc 1111 1111 ...crc 1111 1111 r/w 0xc0d6 spi data port t reserved xxxx xxxx data xxxx xxxx r/w 0xc0d8 spi transmit address address... 0000 0000 ...address 0000 0000 r/w 0xc0da spi transmit count reserved count... 0000 0000 ...count 0000 0000 r/w 0xc0dc spi receive address address... 0000 0000 ...address 0000 0000 r/w 0xc0de spi receive count reserved count... 0000 0000 ...count 0000 0000 r/w 0xc0e0 uart control reserved... 0000 0000 ...reserved scale select baud select uart enable 0000 0111 r 0xc0e2 uart status reserved... 0000 0000 ...reserved receive full transmit full 0000 0000 r/w 0xc0e4 uart data reserved 0000 0000 data 0000 0000 r/w 0xc0e6 pwm control pwm enable reserved prescale select mode select 0000 0000 pwm3 polarity select pwm2 polarity select pwm1 polarity select pwm0 polarity select pwm3 enable pwm2 enable pwm1 enable pwm0 enable 0000 0000 r/w 0xc0e8 pwm maximum count reserved count... 0000 0000 ...count 0000 0000 r/w 0: 0xc0ea 1: 0xc0ee 2: 0xc0f2 3: 0xc0f6 pwm n start reserved address... 0000 0000 ...address 0000 0000 table 142. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 97 of 102 r/w 0: 0xc0ec 1: 0xc0f0 2: 0xc0f4 3: 0xc0f8 pwm n stop reserved address... 0000 0000 ...address 0000 0000 r/w 0xc0fa pwm cycle count count... 0000 0000 ...count 0000 0000 r hpi status port vbus flag id flag reserved sof/eop2 flag reserved sof/eop1 flag reset2 flag mailbox in flag resume2 flag resume1 flag sie2msg sie1msg done2 flag done1 flag reset1 flag mailbox out flag table 142. register summary (continued) r/w address register bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 default high bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default low [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 98 of 102 ordering information ordering code definitions table 143. ordering information ordering code package type aec pb-free temperature range cy7c67300-100axi 100-pin tqfp x ?40 to 85c CY7C67300-100AXA 100-pin tqfp x x ?40 to 85c cy7c67300-100axit 100-pin tqfp, tape and reel x ?40 to 85c CY7C67300-100AXAt 100-pin tqfp, tape and reel x x ?40 to 85c cy3663 development kit cy4640 mass storage reference design x x ?40 to 85c cy 67300 xxx ax - (i, a, e) t tape and reel temperature range: i = industrial; a = automotive; e= extended tqfp pb-free pin count part identifier company code: cy = cypress [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 99 of 102 package diagram figure 12. 100-pin thin plastic quad flat pack (tqfp) a100sa 51-85048 *e [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 100 of 102 acronyms document conventions units of measure table 144. acronyms used in this document acronym description ac alternating current aec automotive electronics council cpu central processing unit crc cyclic redundancy check dc direct current dma direct memory access eeprom electronically erasable programmable read only memory eop end of packet xram external ram memory fifo first in first out gpio general purpose input/output hss high speed serial hpi host port interface ide integrated device electronics i 2 c inter-integrated circuit kvm keyboard-video-mouse otg on-the-go protocol pll phase locked loop por power-on reset pio programmed input/output pwm pulse width modulation ram random access memory rom read only memory spi serial peripheral interface sie serial-interface-engine se0 single ended zero sof start of frame sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus wdt watchdog timer table 145. units of measure symbol unit of measure ns nanosecond vvolt mv millivolt w microwatt a microampere ma milliampere s microsecond ms millisecond mhz megahertz f microfarad pf picofarad mw milliwatt wwatt ppm parts per million c degree celsius [+] feedback
cy7c67300 document #: 38-08015 rev. *k page 101 of 102 document history page document title: cy7c67300 ez-host? programmable embedded usb host and peripheral controller with automotive aec grade support document number: 38-08015 revision ecn orig. of change submission date description of change ** 111872 mul 03/22/02 new data sheet *a 116989 mul 08/23/02 preliminary data sheet *b 125262 mul 04/10/03 added memory map section and ordering information section moved functional register map tables into register section general clean-up *c 126210 mul 05/23/03 added interface description section and power savings and reset section added char data general clean-up *d 127335 kkv 05/29/03 corrected font to enable correct symbol display *e 129395 mul 10/01/03 final data sheet changed memory map section and added clksel to pin description added usb otg logo general clean-up *f 443992 vcs see ecn title changed indicating aec grade added information for aec qualified including part number fixed misc. errors including: table 4-1: uart does not have alternate location section 4.3.4 had incorrect register address table 4-10 had incorrect pin definitions section 4.16.2 changed gpio[31:20] to gpio[31:30] corrected table 7-6 and 7-14 *g 566465 kkvtmp see ecn added the lead free informatio n on the ordering information section. imple- mented the new template with no numbers on the headings. *h 1063560 ari see ecn changed ordering information table to reflect automotive qualification and to meet the mpn part number changes reflected in ecn 884880. changed the ez-host pin diagram figure to reflect the pin changes. edited. *i 2514867 pyrs see ecn to publish in web *j 2544823 bha/aesa 07/ 28/08 updated template. corre cted a18 and a17 pin assignments in tables 6 and 131. *k 3302644 nmma 07/05/11 added cy4640 reference design entry in ordering information table. included table of contents. added ordering code definitions, acronyms, and units of measure. updated package diagram from *c to *e [+] feedback
document #: 38-08015 rev. *k revised july 5, 2011 page 102 of 102 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c67300 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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